From: Abel Vesa <abel.vesa@linaro.org> To: "Andy Gross" <agross@kernel.org>, "Bjorn Andersson" <andersson@kernel.org>, "Konrad Dybcio" <konrad.dybcio@linaro.org>, "Rob Herring" <robh@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Bjorn Helgaas" <bhelgaas@google.com>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "vkoul@kernel.org" <vkoul@kernel.org>, "Kishon Vijay Abraham I" <kishon@kernel.org>, "Manivannan Sadhasivam" <mani@kernel.org>, "Johan Hovold" <johan+linaro@kernel.org> Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Subject: [PATCH v9 10/11] PCI: qcom: Add SM8550 PCIe support Date: Wed, 8 Feb 2023 20:00:19 +0200 [thread overview] Message-ID: <20230208180020.2761766-11-abel.vesa@linaro.org> (raw) In-Reply-To: <20230208180020.2761766-1-abel.vesa@linaro.org> Add compatible for both PCIe found on SM8550. Also add the noc_aggr and cnoc_sf_axi clocks needed by the SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> --- The v8 of this patch is: https://lore.kernel.org/all/20230206212619.3218741-11-abel.vesa@linaro.org/ Changes since v8: * added Johan's R-b tag Changes since v7: * Mentioned the noc_aggr clock in the commit message as well, while using the cnoc_sf_axi instead of cnoc_pcie_sf_axi Changes since v6: * none Changes since v5: * none Changes since v4: * added Mani's R-b tag Changes since v3: * renamed cnoc_pcie_sf_axi to cnoc_sf_axi Changes since v2: * none Changes since v1: * changed the subject line prefix for the patch to match the history, like Bjorn Helgaas suggested. * added Konrad's R-b tag drivers/pci/controller/dwc/pcie-qcom.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a232b04af048..6a70c9c6f98d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -182,10 +182,10 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[14]; int num_clks; struct regulator_bulk_data supplies[2]; - struct reset_control *pci_reset; + struct reset_control *rst; }; struct qcom_pcie_resources_2_9_0 { @@ -1177,9 +1177,9 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) unsigned int idx; int ret; - res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); - if (IS_ERR(res->pci_reset)) - return PTR_ERR(res->pci_reset); + res->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(res->rst)) + return PTR_ERR(res->rst); res->supplies[0].supply = "vdda"; res->supplies[1].supply = "vddpe-3v3"; @@ -1205,9 +1205,11 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[idx++].id = "ddrss_sf_tbu"; res->clks[idx++].id = "aggre0"; res->clks[idx++].id = "aggre1"; + res->clks[idx++].id = "noc_aggr"; res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "cnoc_qx"; + res->clks[idx++].id = "cnoc_sf_axi"; num_opt_clks = idx - num_clks; res->num_clks = idx; @@ -1237,17 +1239,17 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) if (ret < 0) goto err_disable_regulators; - ret = reset_control_assert(res->pci_reset); - if (ret < 0) { - dev_err(dev, "cannot assert pci reset\n"); + ret = reset_control_assert(res->rst); + if (ret) { + dev_err(dev, "reset assert failed (%d)\n", ret); goto err_disable_clocks; } usleep_range(1000, 1500); - ret = reset_control_deassert(res->pci_reset); - if (ret < 0) { - dev_err(dev, "cannot deassert pci reset\n"); + ret = reset_control_deassert(res->rst); + if (ret) { + dev_err(dev, "reset deassert failed (%d)\n", ret); goto err_disable_clocks; } @@ -1841,6 +1843,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, { } }; -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Abel Vesa <abel.vesa@linaro.org> To: "Andy Gross" <agross@kernel.org>, "Bjorn Andersson" <andersson@kernel.org>, "Konrad Dybcio" <konrad.dybcio@linaro.org>, "Rob Herring" <robh@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Bjorn Helgaas" <bhelgaas@google.com>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "vkoul@kernel.org" <vkoul@kernel.org>, "Kishon Vijay Abraham I" <kishon@kernel.org>, "Manivannan Sadhasivam" <mani@kernel.org>, "Johan Hovold" <johan+linaro@kernel.org> Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Subject: [PATCH v9 10/11] PCI: qcom: Add SM8550 PCIe support Date: Wed, 8 Feb 2023 20:00:19 +0200 [thread overview] Message-ID: <20230208180020.2761766-11-abel.vesa@linaro.org> (raw) In-Reply-To: <20230208180020.2761766-1-abel.vesa@linaro.org> Add compatible for both PCIe found on SM8550. Also add the noc_aggr and cnoc_sf_axi clocks needed by the SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> --- The v8 of this patch is: https://lore.kernel.org/all/20230206212619.3218741-11-abel.vesa@linaro.org/ Changes since v8: * added Johan's R-b tag Changes since v7: * Mentioned the noc_aggr clock in the commit message as well, while using the cnoc_sf_axi instead of cnoc_pcie_sf_axi Changes since v6: * none Changes since v5: * none Changes since v4: * added Mani's R-b tag Changes since v3: * renamed cnoc_pcie_sf_axi to cnoc_sf_axi Changes since v2: * none Changes since v1: * changed the subject line prefix for the patch to match the history, like Bjorn Helgaas suggested. * added Konrad's R-b tag drivers/pci/controller/dwc/pcie-qcom.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a232b04af048..6a70c9c6f98d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -182,10 +182,10 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[14]; int num_clks; struct regulator_bulk_data supplies[2]; - struct reset_control *pci_reset; + struct reset_control *rst; }; struct qcom_pcie_resources_2_9_0 { @@ -1177,9 +1177,9 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) unsigned int idx; int ret; - res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); - if (IS_ERR(res->pci_reset)) - return PTR_ERR(res->pci_reset); + res->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(res->rst)) + return PTR_ERR(res->rst); res->supplies[0].supply = "vdda"; res->supplies[1].supply = "vddpe-3v3"; @@ -1205,9 +1205,11 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[idx++].id = "ddrss_sf_tbu"; res->clks[idx++].id = "aggre0"; res->clks[idx++].id = "aggre1"; + res->clks[idx++].id = "noc_aggr"; res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "cnoc_qx"; + res->clks[idx++].id = "cnoc_sf_axi"; num_opt_clks = idx - num_clks; res->num_clks = idx; @@ -1237,17 +1239,17 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) if (ret < 0) goto err_disable_regulators; - ret = reset_control_assert(res->pci_reset); - if (ret < 0) { - dev_err(dev, "cannot assert pci reset\n"); + ret = reset_control_assert(res->rst); + if (ret) { + dev_err(dev, "reset assert failed (%d)\n", ret); goto err_disable_clocks; } usleep_range(1000, 1500); - ret = reset_control_deassert(res->pci_reset); - if (ret < 0) { - dev_err(dev, "cannot deassert pci reset\n"); + ret = reset_control_deassert(res->rst); + if (ret) { + dev_err(dev, "reset deassert failed (%d)\n", ret); goto err_disable_clocks; } @@ -1841,6 +1843,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, { } }; -- 2.34.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2023-02-08 18:01 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-08 18:00 [PATCH v9 00/11] sm8550: Add PCIe HC and PHY support Abel Vesa 2023-02-08 18:00 ` Abel Vesa 2023-02-08 18:00 ` [PATCH v9 01/11] dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 Abel Vesa 2023-02-08 18:00 ` Abel Vesa 2023-02-08 18:00 ` [PATCH v9 02/11] phy: qcom-qmp: pcs: Add v6 register offsets Abel Vesa 2023-02-08 18:00 ` Abel Vesa 2023-02-08 18:00 ` [PATCH v9 03/11] phy: qcom-qmp: pcs: Add v6.20 " Abel Vesa 2023-02-08 18:00 ` Abel Vesa 2023-02-08 18:00 ` [PATCH v9 04/11] phy: qcom-qmp: pcs-pcie: Add v6 " Abel Vesa 2023-02-08 18:00 ` Abel Vesa 2023-02-08 18:00 ` [PATCH v9 05/11] phy: qcom-qmp: pcs-pcie: Add v6.20 " Abel Vesa 2023-02-08 18:00 ` Abel Vesa 2023-02-08 18:00 ` [PATCH v9 06/11] phy: qcom-qmp: qserdes-txrx: " Abel Vesa 2023-02-08 18:00 ` Abel Vesa 2023-02-08 18:00 ` [PATCH v9 07/11] phy: qcom-qmp: qserdes-lane-shared: Add v6 " Abel Vesa 2023-02-08 18:00 ` Abel Vesa 2023-02-08 18:00 ` [PATCH v9 08/11] phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs Abel Vesa 2023-02-08 18:00 ` Abel Vesa 2023-02-08 18:00 ` [PATCH v9 09/11] dt-bindings: PCI: qcom: Add SM8550 compatible Abel Vesa 2023-02-08 18:00 ` Abel Vesa 2023-02-08 18:00 ` Abel Vesa [this message] 2023-02-08 18:00 ` [PATCH v9 10/11] PCI: qcom: Add SM8550 PCIe support Abel Vesa 2023-02-08 18:00 ` [PATCH v9 11/11] arm64: dts: qcom: sm8550: Fix PCIe PHYs and controllers nodes Abel Vesa 2023-02-08 18:00 ` Abel Vesa 2023-02-10 16:58 ` [PATCH v9 00/11] sm8550: Add PCIe HC and PHY support Vinod Koul 2023-02-10 16:58 ` Vinod Koul 2023-03-15 23:34 ` (subset) " Bjorn Andersson 2023-03-15 23:34 ` Bjorn Andersson
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