From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Abhinav Kumar <quic_abhinavk@quicinc.com>
Cc: Stephen Boyd <swboyd@chromium.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Bjorn Andersson <andersson@kernel.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org,
Yassine Oudjana <y.oudjana@protonmail.com>,
Jami Kettunen <jami.kettunen@protonmail.com>
Subject: [PATCH 1/4] drm/msm/a5xx: fix setting of the CP_PREEMPT_ENABLE_LOCAL register
Date: Tue, 14 Feb 2023 05:09:53 +0300 [thread overview]
Message-ID: <20230214020956.164473-2-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20230214020956.164473-1-dmitry.baryshkov@linaro.org>
Rather than writing CP_PREEMPT_ENABLE_GLOBAL twice, follow the vendor
kernel and set CP_PREEMPT_ENABLE_LOCAL register instead. a5xx_submit()
will override it during submission, but let's get the sequence correct.
Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 660ba0db8900..8b2df12d8681 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -151,8 +151,8 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
OUT_RING(ring, 1);
/* Enable local preemption for finegrain preemption */
- OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1);
- OUT_RING(ring, 0x02);
+ OUT_PKT7(ring, CP_PREEMPT_ENABLE_LOCAL, 1);
+ OUT_RING(ring, 0x1);
/* Allow CP_CONTEXT_SWITCH_YIELD packets in the IB2 */
OUT_PKT7(ring, CP_YIELD_ENABLE, 1);
--
2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Abhinav Kumar <quic_abhinavk@quicinc.com>
Cc: freedreno@lists.freedesktop.org,
Yassine Oudjana <y.oudjana@protonmail.com>,
linux-arm-msm@vger.kernel.org,
Bjorn Andersson <andersson@kernel.org>,
dri-devel@lists.freedesktop.org,
Stephen Boyd <swboyd@chromium.org>,
Jami Kettunen <jami.kettunen@protonmail.com>
Subject: [PATCH 1/4] drm/msm/a5xx: fix setting of the CP_PREEMPT_ENABLE_LOCAL register
Date: Tue, 14 Feb 2023 05:09:53 +0300 [thread overview]
Message-ID: <20230214020956.164473-2-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20230214020956.164473-1-dmitry.baryshkov@linaro.org>
Rather than writing CP_PREEMPT_ENABLE_GLOBAL twice, follow the vendor
kernel and set CP_PREEMPT_ENABLE_LOCAL register instead. a5xx_submit()
will override it during submission, but let's get the sequence correct.
Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 660ba0db8900..8b2df12d8681 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -151,8 +151,8 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
OUT_RING(ring, 1);
/* Enable local preemption for finegrain preemption */
- OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1);
- OUT_RING(ring, 0x02);
+ OUT_PKT7(ring, CP_PREEMPT_ENABLE_LOCAL, 1);
+ OUT_RING(ring, 0x1);
/* Allow CP_CONTEXT_SWITCH_YIELD packets in the IB2 */
OUT_PKT7(ring, CP_YIELD_ENABLE, 1);
--
2.30.2
next prev parent reply other threads:[~2023-02-14 2:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-14 2:09 [PATCH 0/4] drm/msm/a5xx: make it work with the latest Mesa Dmitry Baryshkov
2023-02-14 2:09 ` Dmitry Baryshkov
2023-02-14 2:09 ` Dmitry Baryshkov [this message]
2023-02-14 2:09 ` [PATCH 1/4] drm/msm/a5xx: fix setting of the CP_PREEMPT_ENABLE_LOCAL register Dmitry Baryshkov
2023-02-14 2:09 ` [PATCH 2/4] drm/msm/a5xx: fix highest bank bit for a530 Dmitry Baryshkov
2023-02-14 2:09 ` Dmitry Baryshkov
2023-02-14 2:09 ` [PATCH 3/4] drm/msm/a5xx: fix the emptyness check in the preempt code Dmitry Baryshkov
2023-02-14 2:09 ` Dmitry Baryshkov
2023-02-14 2:09 ` [PATCH 4/4] drm/msm/a5xx: fix context faults during ring switch Dmitry Baryshkov
2023-02-14 2:09 ` Dmitry Baryshkov
2023-02-14 17:35 ` Rob Clark
2023-02-14 17:35 ` Rob Clark
2023-02-14 3:51 ` [PATCH 0/4] drm/msm/a5xx: make it work with the latest Mesa Yassine Oudjana
2023-02-14 3:51 ` Yassine Oudjana
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