From: Bin Meng <bmeng@tinylab.org>
To: qemu-devel@nongnu.org
Cc: Weiwei Li <liweiwei@iscas.ac.cn>,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: [PATCH v2 04/18] target/riscv: gdbstub: Minor change for better readability
Date: Tue, 28 Feb 2023 18:40:20 +0800 [thread overview]
Message-ID: <20230228104035.1879882-5-bmeng@tinylab.org> (raw)
In-Reply-To: <20230228104035.1879882-1-bmeng@tinylab.org>
Use a variable 'base_reg' to represent cs->gdb_num_regs so that
the call to ricsv_gen_dynamic_vector_xml() can be placed in one
single line for better readability.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index e57372db38..704f3d6922 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -385,9 +385,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
32, "riscv-32bit-fpu.xml", 0);
}
if (env->misa_ext & RVV) {
+ int base_reg = cs->gdb_num_regs;
gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
- ricsv_gen_dynamic_vector_xml(cs,
- cs->gdb_num_regs),
+ ricsv_gen_dynamic_vector_xml(cs, base_reg),
"riscv-vector.xml", 0);
}
switch (env->misa_mxl_max) {
--
2.25.1
next prev parent reply other threads:[~2023-02-28 10:45 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
2023-02-28 10:40 ` [PATCH v2 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR Bin Meng
2023-02-28 10:40 ` [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() Bin Meng
2023-02-28 12:07 ` liweiwei
2023-03-02 2:50 ` LIU Zhiwei
2023-02-28 10:40 ` [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check Bin Meng
2023-02-28 12:08 ` liweiwei
2023-03-02 2:50 ` LIU Zhiwei
2023-02-28 10:40 ` Bin Meng [this message]
2023-02-28 10:40 ` [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled Bin Meng
2023-03-01 9:52 ` LIU Zhiwei
2023-03-01 9:55 ` Bin Meng
2023-03-01 23:43 ` Palmer Dabbelt
2023-03-02 0:30 ` Bin Meng
2023-03-02 0:58 ` Palmer Dabbelt
2023-03-02 2:43 ` LIU Zhiwei
2023-02-28 10:40 ` [PATCH v2 06/18] target/riscv: Coding style fixes in csr.c Bin Meng
2023-02-28 10:40 ` [PATCH v2 07/18] target/riscv: Use 'bool' type for read_only Bin Meng
2023-02-28 10:40 ` [PATCH v2 08/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit Bin Meng
2023-02-28 10:40 ` [PATCH v2 09/18] target/riscv: Simplify getting RISCVCPU pointer from env Bin Meng
2023-02-28 10:40 ` [PATCH v2 10/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 Bin Meng
2023-02-28 10:40 ` [PATCH v2 11/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() Bin Meng
2023-02-28 13:45 ` [PATCH v2 12/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml Bin Meng
2023-02-28 13:45 ` [PATCH v2 13/18] target/riscv: Allow debugger to access user timer and counter CSRs Bin Meng
2023-02-28 13:45 ` [PATCH v2 14/18] target/riscv: Allow debugger to access seed CSR Bin Meng
2023-02-28 13:45 ` [PATCH v2 15/18] target/riscv: Allow debugger to access {h, s}stateen CSRs Bin Meng
2023-03-02 2:44 ` [PATCH v2 15/18] target/riscv: Allow debugger to access {h,s}stateen CSRs LIU Zhiwei
2023-02-28 13:45 ` [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs Bin Meng
2023-03-02 2:44 ` LIU Zhiwei
2023-02-28 13:45 ` [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate() Bin Meng
2023-03-02 2:45 ` LIU Zhiwei
2023-02-28 13:45 ` [PATCH v2 18/18] target/riscv: Group all predicate() routines together Bin Meng
2023-03-02 2:47 ` LIU Zhiwei
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