From: arinc9.unal@gmail.com To: "Sean Wang" <sean.wang@mediatek.com>, "Landen Chao" <Landen.Chao@mediatek.com>, "DENG Qingfang" <dqfext@gmail.com>, "Andrew Lunn" <andrew@lunn.ch>, "Florian Fainelli" <f.fainelli@gmail.com>, "Vladimir Oltean" <olteanv@gmail.com>, "David S. Miller" <davem@davemloft.net>, "Eric Dumazet" <edumazet@google.com>, "Jakub Kicinski" <kuba@kernel.org>, "Paolo Abeni" <pabeni@redhat.com>, "Matthias Brugger" <matthias.bgg@gmail.com>, "AngeloGioacchino Del Regno" <angelogioacchino.delregno@collabora.com>, "Russell King" <rmk+kernel@armlinux.org.uk>, "René van Dorst" <opensource@vdorst.com> Cc: "Arınç ÜNAL" <arinc.unal@arinc9.com>, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net 2/2] net: dsa: mt7530: set PLL frequency only when trgmii is used Date: Wed, 8 Mar 2023 01:03:28 +0300 [thread overview] Message-ID: <20230307220328.11186-2-arinc.unal@arinc9.com> (raw) In-Reply-To: <20230307220328.11186-1-arinc.unal@arinc9.com> From: Arınç ÜNAL <arinc.unal@arinc9.com> As my testing on the MCM MT7530 switch on MT7621 SoC shows, setting the PLL frequency does not affect MII modes other than trgmii on port 5 and port 6. So the assumption is that the operation here called "setting the PLL frequency" actually sets the frequency of the TRGMII TX clock. Make it so that it is set only when the trgmii mode is used. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> --- drivers/net/dsa/mt7530.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index b1a79460df0e..961306c1ac14 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -430,8 +430,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) switch (interface) { case PHY_INTERFACE_MODE_RGMII: trgint = 0; - /* PLL frequency: 125MHz */ - ncpo1 = 0x0c80; break; case PHY_INTERFACE_MODE_TRGMII: trgint = 1; -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: arinc9.unal@gmail.com To: "Sean Wang" <sean.wang@mediatek.com>, "Landen Chao" <Landen.Chao@mediatek.com>, "DENG Qingfang" <dqfext@gmail.com>, "Andrew Lunn" <andrew@lunn.ch>, "Florian Fainelli" <f.fainelli@gmail.com>, "Vladimir Oltean" <olteanv@gmail.com>, "David S. Miller" <davem@davemloft.net>, "Eric Dumazet" <edumazet@google.com>, "Jakub Kicinski" <kuba@kernel.org>, "Paolo Abeni" <pabeni@redhat.com>, "Matthias Brugger" <matthias.bgg@gmail.com>, "AngeloGioacchino Del Regno" <angelogioacchino.delregno@collabora.com>, "Russell King" <rmk+kernel@armlinux.org.uk>, "René van Dorst" <opensource@vdorst.com> Cc: "Arınç ÜNAL" <arinc.unal@arinc9.com>, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net 2/2] net: dsa: mt7530: set PLL frequency only when trgmii is used Date: Wed, 8 Mar 2023 01:03:28 +0300 [thread overview] Message-ID: <20230307220328.11186-2-arinc.unal@arinc9.com> (raw) In-Reply-To: <20230307220328.11186-1-arinc.unal@arinc9.com> From: Arınç ÜNAL <arinc.unal@arinc9.com> As my testing on the MCM MT7530 switch on MT7621 SoC shows, setting the PLL frequency does not affect MII modes other than trgmii on port 5 and port 6. So the assumption is that the operation here called "setting the PLL frequency" actually sets the frequency of the TRGMII TX clock. Make it so that it is set only when the trgmii mode is used. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> --- drivers/net/dsa/mt7530.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index b1a79460df0e..961306c1ac14 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -430,8 +430,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) switch (interface) { case PHY_INTERFACE_MODE_RGMII: trgint = 0; - /* PLL frequency: 125MHz */ - ncpo1 = 0x0c80; break; case PHY_INTERFACE_MODE_TRGMII: trgint = 1; -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-03-07 22:03 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-07 22:03 [PATCH net 1/2] net: dsa: mt7530: remove now incorrect comment regarding port 5 arinc9.unal 2023-03-07 22:03 ` arinc9.unal 2023-03-07 22:03 ` arinc9.unal [this message] 2023-03-07 22:03 ` [PATCH net 2/2] net: dsa: mt7530: set PLL frequency only when trgmii is used arinc9.unal 2023-03-07 23:33 ` Vladimir Oltean 2023-03-07 23:33 ` Vladimir Oltean 2023-03-08 8:50 ` Arınç ÜNAL 2023-03-08 8:50 ` Arınç ÜNAL 2023-03-07 22:06 ` [PATCH net 1/2] net: dsa: mt7530: remove now incorrect comment regarding port 5 Vladimir Oltean 2023-03-07 22:06 ` Vladimir Oltean 2023-03-07 22:21 ` Arınç ÜNAL 2023-03-07 22:21 ` Arınç ÜNAL
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