All of lore.kernel.org
 help / color / mirror / Atom feed
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
	bmeng@tinylab.org, liweiwei@iscas.ac.cn,
	zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH for-8.1 11/17] target/riscv/cpu.c: move riscv_cpu_validate_v() up
Date: Wed,  8 Mar 2023 17:19:19 -0300	[thread overview]
Message-ID: <20230308201925.258223-12-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com>

riscv_cpu_validate_set_extensions() will play a future role in
write_misa(). First we need to ensure that this function is validating
first and setting cfg values later. At this moment this is not the case
of the RVV validation.

Move RVV validation up. Leave the 'ext |= RVV' where it is - next patch
has plans for it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4988fd4d4b..48838471b8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1111,6 +1111,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         }
     }
 
+    if (cpu->cfg.ext_v) {
+        riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
+        if (local_err != NULL) {
+            error_propagate(errp, local_err);
+            return;
+        }
+    }
+
     if (cpu->cfg.ext_zk) {
         cpu->cfg.ext_zkn = true;
         cpu->cfg.ext_zkr = true;
@@ -1165,12 +1173,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         ext |= RVH;
     }
     if (cpu->cfg.ext_v) {
-        riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
-        if (local_err != NULL) {
-            error_propagate(errp, local_err);
-            return;
-        }
-
         ext |= RVV;
     }
     if (cpu->cfg.ext_j) {
-- 
2.39.2



  parent reply	other threads:[~2023-03-08 20:21 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-08 20:19 [PATCH for-8.1 00/17] centralize CPU extensions logic Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 01/17] target/riscv/cpu.c: add riscv_cpu_validate_v() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 02/17] target/riscv/cpu.c: remove set_vext_version() Daniel Henrique Barboza
2023-03-09  7:28   ` LIU Zhiwei
2023-03-08 20:19 ` [PATCH for-8.1 03/17] target/riscv/cpu.c: remove set_priv_version() Daniel Henrique Barboza
2023-03-09  7:28   ` LIU Zhiwei
2023-03-09 16:22     ` Daniel Henrique Barboza
2023-03-10  0:18       ` Alistair Francis
2023-03-08 20:19 ` [PATCH for-8.1 04/17] target/riscv: add PRIV_VERSION_LATEST macro Daniel Henrique Barboza
2023-03-08 23:00   ` Richard Henderson
2023-03-09 15:59     ` Daniel Henrique Barboza
2023-03-09  7:31   ` LIU Zhiwei
2023-03-08 20:19 ` [PATCH for-8.1 05/17] target/riscv/cpu.c: add riscv_cpu_validate_priv_spec() Daniel Henrique Barboza
2023-03-08 23:06   ` Richard Henderson
2023-03-08 20:19 ` [PATCH for-8.1 06/17] target/riscv: move realize() validations to riscv_cpu_validate_set_extensions() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 07/17] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 08/17] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 09/17] target/riscv/cpu.c: set cpu config in set_misa() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 10/17] target/riscv/cpu.c: redesign register_cpu_props() Daniel Henrique Barboza
2023-03-08 20:19 ` Daniel Henrique Barboza [this message]
2023-03-08 20:19 ` [PATCH for-8.1 12/17] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 13/17] target/riscv/cpu.c: split riscv_cpu_validate_priv_spec() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 14/17] target/riscv/cpu.c: do not allow RVE to be set Daniel Henrique Barboza
2023-03-09  7:10   ` LIU Zhiwei
2023-03-09 16:23     ` Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 15/17] target/riscv: add RVG Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 16/17] target/riscv: do not allow RVG in write_misa() Daniel Henrique Barboza
2023-03-08 20:19 ` [PATCH for-8.1 17/17] target/riscv: rework write_misa() Daniel Henrique Barboza
2023-03-09  7:27   ` LIU Zhiwei
2023-03-09  7:40     ` LIU Zhiwei
2023-03-09 16:35       ` Daniel Henrique Barboza
2023-03-09 16:33     ` Daniel Henrique Barboza
2023-03-09 21:14 ` [PATCH for-8.1 00/17] centralize CPU extensions logic Daniel Henrique Barboza

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230308201925.258223-12-dbarboza@ventanamicro.com \
    --to=dbarboza@ventanamicro.com \
    --cc=alistair.francis@wdc.com \
    --cc=bmeng@tinylab.org \
    --cc=liweiwei@iscas.ac.cn \
    --cc=palmer@rivosinc.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=zhiwei_liu@linux.alibaba.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.