From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Vincent Chen <vincent.chen@sifive.com>, Conor Dooley <conor.dooley@microchip.com>, Guo Ren <guoren@kernel.org>, Al Viro <viro@zeniv.linux.org.uk>, Andrew Bresticker <abrestic@rivosinc.com> Subject: [PATCH -next v15 15/19] riscv: signal: validate altstack to reflect Vector Date: Fri, 17 Mar 2023 11:35:34 +0000 [thread overview] Message-ID: <20230317113538.10878-16-andy.chiu@sifive.com> (raw) In-Reply-To: <20230317113538.10878-1-andy.chiu@sifive.com> Some extensions, such as Vector, dynamically change footprint on a signal frame, so MINSIGSTKSZ is no longer accurate. For example, an RV64V implementation with vlen = 512 may occupy 2K + 40 + 12 Bytes of a signal frame with the upcoming support. And processes that do not execute any vector instructions do not need to reserve the extra sigframe. So we need a way to guard the allocation size of the sigframe at process runtime according to current status of V. Thus, provide the function sigaltstack_size_valid() to validate its size based on current allocation status of supported extensions. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- arch/riscv/kernel/signal.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index d2d9232498ca..b8ad9a7fc0ad 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -494,3 +494,11 @@ void __init init_rt_signal_env(void) */ signal_minsigstksz = get_rt_frame_size(true); } + +#ifdef CONFIG_DYNAMIC_SIGFRAME +bool sigaltstack_size_valid(size_t ss_size) +{ + return ss_size > get_rt_frame_size(false); +} +#endif /* CONFIG_DYNAMIC_SIGFRAME */ + -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Vincent Chen <vincent.chen@sifive.com>, Conor Dooley <conor.dooley@microchip.com>, Guo Ren <guoren@kernel.org>, Al Viro <viro@zeniv.linux.org.uk>, Andrew Bresticker <abrestic@rivosinc.com> Subject: [PATCH -next v15 15/19] riscv: signal: validate altstack to reflect Vector Date: Fri, 17 Mar 2023 11:35:34 +0000 [thread overview] Message-ID: <20230317113538.10878-16-andy.chiu@sifive.com> (raw) In-Reply-To: <20230317113538.10878-1-andy.chiu@sifive.com> Some extensions, such as Vector, dynamically change footprint on a signal frame, so MINSIGSTKSZ is no longer accurate. For example, an RV64V implementation with vlen = 512 may occupy 2K + 40 + 12 Bytes of a signal frame with the upcoming support. And processes that do not execute any vector instructions do not need to reserve the extra sigframe. So we need a way to guard the allocation size of the sigframe at process runtime according to current status of V. Thus, provide the function sigaltstack_size_valid() to validate its size based on current allocation status of supported extensions. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- arch/riscv/kernel/signal.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index d2d9232498ca..b8ad9a7fc0ad 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -494,3 +494,11 @@ void __init init_rt_signal_env(void) */ signal_minsigstksz = get_rt_frame_size(true); } + +#ifdef CONFIG_DYNAMIC_SIGFRAME +bool sigaltstack_size_valid(size_t ss_size) +{ + return ss_size > get_rt_frame_size(false); +} +#endif /* CONFIG_DYNAMIC_SIGFRAME */ + -- 2.17.1
next prev parent reply other threads:[~2023-03-17 11:38 UTC|newest] Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-17 11:35 [PATCH -next v15 00/19] riscv: Add vector ISA support Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 11:35 ` [PATCH -next v15 01/19] riscv: Rename __switch_to_aux() -> fpu Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 11:35 ` [PATCH -next v15 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 11:35 ` [PATCH -next v15 03/19] riscv: Add new csr defines related to vector extension Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 11:35 ` [PATCH -next v15 04/19] riscv: Clear vector regfile on bootup Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 11:35 ` [PATCH -next v15 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 11:35 ` [PATCH -next v15 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 11:35 ` [PATCH -next v15 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-20 13:02 ` Conor Dooley 2023-03-20 13:02 ` Conor Dooley 2023-03-17 11:35 ` [PATCH -next v15 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-20 13:05 ` Conor Dooley 2023-03-20 13:05 ` Conor Dooley 2023-03-20 14:46 ` Andy Chiu 2023-03-20 14:46 ` Andy Chiu 2023-03-20 14:54 ` Conor Dooley 2023-03-20 14:54 ` Conor Dooley 2023-03-22 1:54 ` Guo Ren 2023-03-22 1:54 ` Guo Ren 2023-03-23 10:21 ` Björn Töpel 2023-03-23 10:21 ` Björn Töpel 2023-03-17 11:35 ` [PATCH -next v15 09/19] riscv: Add task switch support for vector Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-20 13:07 ` Conor Dooley 2023-03-20 13:07 ` Conor Dooley 2023-03-23 10:23 ` Björn Töpel 2023-03-23 10:23 ` Björn Töpel 2023-03-17 11:35 ` [PATCH -next v15 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-20 13:27 ` Conor Dooley 2023-03-20 13:27 ` Conor Dooley 2023-03-23 10:29 ` Björn Töpel 2023-03-23 10:29 ` Björn Töpel 2023-03-17 11:35 ` [PATCH -next v15 11/19] riscv: Add ptrace vector support Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 11:35 ` [PATCH -next v15 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 11:35 ` [PATCH -next v15 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-20 13:36 ` Conor Dooley 2023-03-20 13:36 ` Conor Dooley 2023-03-23 7:50 ` Andy Chiu 2023-03-23 7:50 ` Andy Chiu 2023-03-17 11:35 ` [PATCH -next v15 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-23 10:36 ` Björn Töpel 2023-03-23 10:36 ` Björn Töpel 2023-03-23 14:39 ` Guo Ren 2023-03-23 14:39 ` Guo Ren 2023-03-17 11:35 ` Andy Chiu [this message] 2023-03-17 11:35 ` [PATCH -next v15 15/19] riscv: signal: validate altstack to reflect Vector Andy Chiu 2023-03-20 13:40 ` Conor Dooley 2023-03-20 13:40 ` Conor Dooley 2023-03-17 11:35 ` [PATCH -next v15 16/19] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 11:35 ` [PATCH -next v15 17/19] riscv: kvm: Add V extension to KVM ISA Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 11:54 ` Anup Patel 2023-03-17 11:54 ` Anup Patel 2023-03-17 11:35 ` [PATCH -next v15 18/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 12:02 ` Anup Patel 2023-03-17 12:02 ` Anup Patel 2023-03-17 11:35 ` [PATCH -next v15 19/19] riscv: Enable Vector code to be built Andy Chiu 2023-03-17 11:35 ` Andy Chiu 2023-03-17 15:46 ` Nathan Chancellor 2023-03-17 15:46 ` Nathan Chancellor 2023-03-20 13:47 ` Conor Dooley 2023-03-20 13:47 ` Conor Dooley 2023-03-23 10:44 ` [PATCH -next v15 00/19] riscv: Add vector ISA support Björn Töpel 2023-03-23 10:44 ` Björn Töpel
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230317113538.10878-16-andy.chiu@sifive.com \ --to=andy.chiu@sifive.com \ --cc=abrestic@rivosinc.com \ --cc=anup@brainfault.org \ --cc=aou@eecs.berkeley.edu \ --cc=atishp@atishpatra.org \ --cc=conor.dooley@microchip.com \ --cc=greentime.hu@sifive.com \ --cc=guoren@kernel.org \ --cc=guoren@linux.alibaba.com \ --cc=kvm-riscv@lists.infradead.org \ --cc=kvm@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=vincent.chen@sifive.com \ --cc=vineetg@rivosinc.com \ --cc=viro@zeniv.linux.org.uk \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.