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From: Andre Przywara <andre.przywara@arm.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Chen-Yu Tsai <wens@csie.org>,
	Samuel Holland <samuel@sholland.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org,
	"Conor Dooley" <conor@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"András Szemzö" <szemzo.andras@gmail.com>,
	"Icenowy Zheng" <uwu@icenowy.me>,
	"Fabien Poussin" <fabien.poussin@gmail.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
	"Belisko Marek" <marek.belisko@gmail.com>
Subject: [PATCH v2 1/4] dts: add riscv include prefix link
Date: Mon, 20 Mar 2023 00:52:46 +0000	[thread overview]
Message-ID: <20230320005249.13403-2-andre.przywara@arm.com> (raw)
In-Reply-To: <20230320005249.13403-1-andre.przywara@arm.com>

The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical
die as their R528/T113-s siblings with ARM Cortex-A7 cores.

To allow sharing the basic SoC .dtsi files across those two
architectures as well, introduce a symlink to the RISC-V DT directory.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 scripts/dtc/include-prefixes/riscv | 1 +
 1 file changed, 1 insertion(+)
 create mode 120000 scripts/dtc/include-prefixes/riscv

diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv
new file mode 120000
index 0000000000000..2025094189380
--- /dev/null
+++ b/scripts/dtc/include-prefixes/riscv
@@ -0,0 +1 @@
+../../../arch/riscv/boot/dts
\ No newline at end of file
-- 
2.35.7


WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Chen-Yu Tsai <wens@csie.org>,
	Samuel Holland <samuel@sholland.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: devicetree@vger.kernel.org, "Albert Ou" <aou@eecs.berkeley.edu>,
	"András Szemzö" <szemzo.andras@gmail.com>,
	"Belisko Marek" <marek.belisko@gmail.com>,
	"Fabien Poussin" <fabien.poussin@gmail.com>,
	linux-kernel@vger.kernel.org, "Conor Dooley" <conor@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/4] dts: add riscv include prefix link
Date: Mon, 20 Mar 2023 00:52:46 +0000	[thread overview]
Message-ID: <20230320005249.13403-2-andre.przywara@arm.com> (raw)
In-Reply-To: <20230320005249.13403-1-andre.przywara@arm.com>

The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical
die as their R528/T113-s siblings with ARM Cortex-A7 cores.

To allow sharing the basic SoC .dtsi files across those two
architectures as well, introduce a symlink to the RISC-V DT directory.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 scripts/dtc/include-prefixes/riscv | 1 +
 1 file changed, 1 insertion(+)
 create mode 120000 scripts/dtc/include-prefixes/riscv

diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv
new file mode 120000
index 0000000000000..2025094189380
--- /dev/null
+++ b/scripts/dtc/include-prefixes/riscv
@@ -0,0 +1 @@
+../../../arch/riscv/boot/dts
\ No newline at end of file
-- 
2.35.7


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Chen-Yu Tsai <wens@csie.org>,
	Samuel Holland <samuel@sholland.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org,
	"Conor Dooley" <conor@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"András Szemzö" <szemzo.andras@gmail.com>,
	"Icenowy Zheng" <uwu@icenowy.me>,
	"Fabien Poussin" <fabien.poussin@gmail.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
	"Belisko Marek" <marek.belisko@gmail.com>
Subject: [PATCH v2 1/4] dts: add riscv include prefix link
Date: Mon, 20 Mar 2023 00:52:46 +0000	[thread overview]
Message-ID: <20230320005249.13403-2-andre.przywara@arm.com> (raw)
In-Reply-To: <20230320005249.13403-1-andre.przywara@arm.com>

The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical
die as their R528/T113-s siblings with ARM Cortex-A7 cores.

To allow sharing the basic SoC .dtsi files across those two
architectures as well, introduce a symlink to the RISC-V DT directory.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 scripts/dtc/include-prefixes/riscv | 1 +
 1 file changed, 1 insertion(+)
 create mode 120000 scripts/dtc/include-prefixes/riscv

diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv
new file mode 120000
index 0000000000000..2025094189380
--- /dev/null
+++ b/scripts/dtc/include-prefixes/riscv
@@ -0,0 +1 @@
+../../../arch/riscv/boot/dts
\ No newline at end of file
-- 
2.35.7


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2023-03-20  0:53 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-20  0:52 [PATCH v2 0/4] ARM: dts: sunxi: Add MangoPi MQ-R board support Andre Przywara
2023-03-20  0:52 ` Andre Przywara
2023-03-20  0:52 ` Andre Przywara
2023-03-20  0:52 ` Andre Przywara [this message]
2023-03-20  0:52   ` [PATCH v2 1/4] dts: add riscv include prefix link Andre Przywara
2023-03-20  0:52   ` Andre Przywara
2023-03-20  0:52 ` [PATCH v2 2/4] ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi Andre Przywara
2023-03-20  0:52   ` Andre Przywara
2023-03-20  0:52   ` Andre Przywara
2023-03-23 21:17   ` Jernej Škrabec
2023-03-23 21:17     ` Jernej Škrabec
2023-03-23 21:17     ` Jernej Škrabec
2023-03-20  0:52 ` [PATCH v2 3/4] dt-bindings: arm: sunxi: document MangoPi MQ-R board names Andre Przywara
2023-03-20  0:52   ` Andre Przywara
2023-03-20  0:52   ` Andre Przywara
2023-03-20  6:51   ` Krzysztof Kozlowski
2023-03-20  6:51     ` Krzysztof Kozlowski
2023-03-20  6:51     ` Krzysztof Kozlowski
2023-03-20  0:52 ` [PATCH v2 4/4] ARM: dts: sunxi: add MangoPi MQ-R-T113 board Andre Przywara
2023-03-20  0:52   ` Andre Przywara
2023-03-20  0:52   ` Andre Przywara
2023-03-23 21:21   ` Jernej Škrabec
2023-03-23 21:21     ` Jernej Škrabec
2023-03-23 21:21     ` Jernej Škrabec
2023-03-27  8:30   ` Belisko Marek
2023-03-27  8:30     ` Belisko Marek
2023-03-27  8:30     ` Belisko Marek
2023-03-27  9:21     ` Andre Przywara
2023-03-27  9:21       ` Andre Przywara
2023-03-27  9:21       ` Andre Przywara
2023-03-27 20:46 ` [PATCH v2 0/4] ARM: dts: sunxi: Add MangoPi MQ-R board support Jernej Škrabec
2023-03-27 20:46   ` Jernej Škrabec
2023-03-27 20:46   ` Jernej Škrabec

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