From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH 14/19] target/riscv: remove cpu->cfg.ext_j
Date: Mon, 27 Mar 2023 09:42:42 -0300 [thread overview]
Message-ID: <20230327124247.106595-15-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com>
Create a new "j" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
replaced with riscv_has_ext(env, RVJ).
Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 6 +++---
target/riscv/cpu.h | 1 -
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 90c8fc0f30..8589f7bd67 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1119,7 +1119,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_v) {
ext |= RVV;
}
- if (riscv_cpu_cfg(env)->ext_j) {
+ if (riscv_has_ext(env, RVJ)) {
ext |= RVJ;
}
@@ -1452,6 +1452,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVU, .enabled = true},
{.name = "h", .description = "Hypervisor",
.misa_bit = RVH, .enabled = true},
+ {.name = "x-j", .description = "Dynamic translated languages",
+ .misa_bit = RVJ, .enabled = false},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1548,7 +1550,6 @@ static Property riscv_cpu_extensions[] = {
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
- DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
@@ -1580,7 +1581,6 @@ static void register_cpu_props(Object *obj)
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV;
- cpu->cfg.ext_j = misa_ext & RVJ;
/*
* We don't want to set the default riscv_cpu_extensions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f3cb28443c..43a40ba950 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -419,7 +419,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_j;
bool ext_v;
bool ext_zba;
bool ext_zbb;
--
2.39.2
next prev parent reply other threads:[~2023-03-27 12:44 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-27 12:42 [PATCH 00/19] remove MISA ext_N flags from cpu->cfg Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 01/19] target/riscv: sync env->misa_ext* with cpu->cfg in realize() Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 02/19] target/riscv: remove MISA properties from isa_edata_arr[] Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 03/19] target/riscv: introduce riscv_cpu_add_misa_properties() Daniel Henrique Barboza
2023-03-27 18:43 ` Richard Henderson
2023-03-27 18:59 ` Daniel Henrique Barboza
2023-03-27 18:52 ` Richard Henderson
2023-03-27 22:15 ` Daniel Henrique Barboza
2023-03-27 22:27 ` Richard Henderson
2023-03-27 12:42 ` [PATCH 04/19] target/riscv: remove cpu->cfg.ext_a Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 05/19] target/riscv: remove cpu->cfg.ext_c Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 06/19] target/riscv: remove cpu->cfg.ext_d Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 07/19] target/riscv: remove cpu->cfg.ext_f Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 08/19] target/riscv: remove cpu->cfg.ext_i Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 09/19] target/riscv: remove cpu->cfg.ext_e Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 10/19] target/riscv: remove cpu->cfg.ext_m Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 11/19] target/riscv: remove cpu->cfg.ext_s Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 12/19] target/riscv: remove cpu->cfg.ext_u Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 13/19] target/riscv: remove cpu->cfg.ext_h Daniel Henrique Barboza
2023-03-27 12:42 ` Daniel Henrique Barboza [this message]
2023-03-27 12:42 ` [PATCH 15/19] target/riscv: remove cpu->cfg.ext_v Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 16/19] target/riscv: remove riscv_cpu_sync_misa_cfg() Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 17/19] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 18/19] target/riscv: add RVG and remove cpu->cfg.ext_g Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 19/19] target/riscv/cpu.c: redesign register_cpu_props() Daniel Henrique Barboza
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