From: Bartosz Golaszewski <brgl@bgdev.pl> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski <bartosz.golaszewski@linaro.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com> Subject: [PATCH 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Date: Tue, 28 Mar 2023 21:36:26 +0200 [thread overview] Message-ID: <20230328193632.226095-2-brgl@bgdev.pl> (raw) In-Reply-To: <20230328193632.226095-1-brgl@bgdev.pl> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Add bindings for the Qualcomm Graphics Clock control module present on sa8775p platforms. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> --- .../bindings/clock/qcom,sa8775p-gpucc.yaml | 61 +++++++++++++++++++ .../dt-bindings/clock/qcom,sa8775p-gpucc.h | 50 +++++++++++++++ 2 files changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sa8775p-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml new file mode 100644 index 000000000000..203802f81738 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SA8775P + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sa8775p-gpucc.h + +properties: + compatible: + enum: + - qcom,sa8775p-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + - description: SNoC DVM GFX source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sa8775p-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sa8775p-gpucc.h b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h new file mode 100644 index 000000000000..a5fd784b1ea2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H +#define _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CB_CLK 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_FF_CLK 5 +#define GPU_CC_CX_GMU_CLK 6 +#define GPU_CC_CX_SNOC_DVM_CLK 7 +#define GPU_CC_CXO_AON_CLK 8 +#define GPU_CC_CXO_CLK 9 +#define GPU_CC_DEMET_CLK 10 +#define GPU_CC_DEMET_DIV_CLK_SRC 11 +#define GPU_CC_FF_CLK_SRC 12 +#define GPU_CC_GMU_CLK_SRC 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 15 +#define GPU_CC_HUB_AON_CLK 16 +#define GPU_CC_HUB_CLK_SRC 17 +#define GPU_CC_HUB_CX_INT_CLK 18 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 19 +#define GPU_CC_MEMNOC_GFX_CLK 20 +#define GPU_CC_SLEEP_CLK 21 +#define GPU_CC_XO_CLK_SRC 22 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_FF_BCR 4 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 5 +#define GPUCC_GPU_CC_GMU_BCR 6 +#define GPUCC_GPU_CC_GX_BCR 7 +#define GPUCC_GPU_CC_XO_BCR 8 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +#endif /* _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H */ -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: Bartosz Golaszewski <brgl@bgdev.pl> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski <bartosz.golaszewski@linaro.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com> Subject: [PATCH 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Date: Tue, 28 Mar 2023 21:36:26 +0200 [thread overview] Message-ID: <20230328193632.226095-2-brgl@bgdev.pl> (raw) In-Reply-To: <20230328193632.226095-1-brgl@bgdev.pl> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Add bindings for the Qualcomm Graphics Clock control module present on sa8775p platforms. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> --- .../bindings/clock/qcom,sa8775p-gpucc.yaml | 61 +++++++++++++++++++ .../dt-bindings/clock/qcom,sa8775p-gpucc.h | 50 +++++++++++++++ 2 files changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sa8775p-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml new file mode 100644 index 000000000000..203802f81738 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SA8775P + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sa8775p-gpucc.h + +properties: + compatible: + enum: + - qcom,sa8775p-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + - description: SNoC DVM GFX source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sa8775p-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sa8775p-gpucc.h b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h new file mode 100644 index 000000000000..a5fd784b1ea2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H +#define _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CB_CLK 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_FF_CLK 5 +#define GPU_CC_CX_GMU_CLK 6 +#define GPU_CC_CX_SNOC_DVM_CLK 7 +#define GPU_CC_CXO_AON_CLK 8 +#define GPU_CC_CXO_CLK 9 +#define GPU_CC_DEMET_CLK 10 +#define GPU_CC_DEMET_DIV_CLK_SRC 11 +#define GPU_CC_FF_CLK_SRC 12 +#define GPU_CC_GMU_CLK_SRC 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 15 +#define GPU_CC_HUB_AON_CLK 16 +#define GPU_CC_HUB_CLK_SRC 17 +#define GPU_CC_HUB_CX_INT_CLK 18 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 19 +#define GPU_CC_MEMNOC_GFX_CLK 20 +#define GPU_CC_SLEEP_CLK 21 +#define GPU_CC_XO_CLK_SRC 22 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_FF_BCR 4 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 5 +#define GPUCC_GPU_CC_GMU_BCR 6 +#define GPUCC_GPU_CC_GX_BCR 7 +#define GPUCC_GPU_CC_XO_BCR 8 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +#endif /* _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H */ -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-03-28 19:36 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-28 19:36 [PATCH 0/7] arm64: dts: qcom: sa8775p: add more IOMMUs Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski [this message] 2023-03-28 19:36 ` [PATCH 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Bartosz Golaszewski 2023-03-29 8:30 ` Krzysztof Kozlowski 2023-03-29 8:30 ` Krzysztof Kozlowski 2023-03-28 19:36 ` [PATCH 2/7] clk: qcom: add the GPUCC driver for sa8775p Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-29 2:15 ` Stephen Boyd 2023-03-29 2:15 ` Stephen Boyd 2023-04-06 11:20 ` Bartosz Golaszewski 2023-04-06 11:20 ` Bartosz Golaszewski 2023-04-10 19:09 ` Stephen Boyd 2023-04-10 19:09 ` Stephen Boyd 2023-03-29 11:30 ` Konrad Dybcio 2023-03-29 11:30 ` Konrad Dybcio 2023-03-28 19:36 ` [PATCH 3/7] arm64: defconfig: enable the SA8775P GPUCC driver Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-29 8:33 ` Krzysztof Kozlowski 2023-03-29 8:33 ` Krzysztof Kozlowski 2023-04-06 13:28 ` Dmitry Baryshkov 2023-04-06 13:28 ` Dmitry Baryshkov 2023-03-28 19:36 ` [PATCH 4/7] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-29 8:31 ` Krzysztof Kozlowski 2023-03-29 8:31 ` Krzysztof Kozlowski 2023-04-03 20:41 ` Rob Herring 2023-04-03 20:41 ` Rob Herring 2023-04-03 22:38 ` Konrad Dybcio 2023-04-03 22:38 ` Konrad Dybcio 2023-03-28 19:36 ` [PATCH 5/7] arm64: dts: qcom: sa8775p: add the pcie smmu node Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-29 11:33 ` Konrad Dybcio 2023-03-29 11:33 ` Konrad Dybcio 2023-03-28 19:36 ` [PATCH 6/7] arm64: dts: qcom: sa8775p: add the GPU clock controller node Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski 2023-03-29 11:31 ` Konrad Dybcio 2023-03-29 11:31 ` Konrad Dybcio 2023-03-28 19:36 ` [PATCH 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Bartosz Golaszewski 2023-03-28 19:36 ` Bartosz Golaszewski
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