From: Prabhakar <prabhakar.csengg@gmail.com> To: Arnd Bergmann <arnd@arndb.de>, Conor Dooley <conor.dooley@microchip.com>, Geert Uytterhoeven <geert+renesas@glider.be>, Heiko Stuebner <heiko@sntech.de>, Guo Ren <guoren@kernel.org>, Andrew Jones <ajones@ventanamicro.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Samuel Holland <samuel@sholland.org>, linux-riscv@lists.infradead.org Cc: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh@kernel.org> Subject: [PATCH v7 4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Date: Thu, 30 Mar 2023 21:42:15 +0100 [thread overview] Message-ID: <20230330204217.47666-5-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw) In-Reply-To: <20230330204217.47666-1-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Add DT binding documentation for L2 cache controller found on RZ/Five SoC. The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. The AX45MP core has an L2 cache controller, this patch describes the L2 cache block. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> --- v6 -> v7 * No Change v5 -> v6 * Included RB tag from Rob v4 -> v5 * Dropped L2 cache configuration properties * Dropped PMA configuration properties * Ordered the required list to match the properties list RFC v3 -> v4 * Dropped l2 cache configuration parameters * s/larger/large * Added minItems/maxItems for andestech,pma-regions --- .../cache/andestech,ax45mp-cache.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml new file mode 100644 index 000000000000..9ab5f0c435d4 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andestech AX45MP L2 Cache Controller + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: + A level-2 cache (L2C) is used to improve the system performance by providing + a large amount of cache line entries and reasonable access delays. The L2C + is shared between cores, and a non-inclusive non-exclusive policy is used. + +select: + properties: + compatible: + contains: + enum: + - andestech,ax45mp-cache + + required: + - compatible + +properties: + compatible: + items: + - const: andestech,ax45mp-cache + - const: cache + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cache-line-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + enum: [131072, 262144, 524288, 1048576, 2097152] + + cache-unified: true + + next-level-cache: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - cache-line-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + cache-controller@2010000 { + compatible = "andestech,ax45mp-cache", "cache"; + reg = <0x13400000 0x100000>; + interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <262144>; + cache-unified; + }; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Prabhakar <prabhakar.csengg@gmail.com> To: Arnd Bergmann <arnd@arndb.de>, Conor Dooley <conor.dooley@microchip.com>, Geert Uytterhoeven <geert+renesas@glider.be>, Heiko Stuebner <heiko@sntech.de>, Guo Ren <guoren@kernel.org>, Andrew Jones <ajones@ventanamicro.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Samuel Holland <samuel@sholland.org>, linux-riscv@lists.infradead.org Cc: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh@kernel.org> Subject: [PATCH v7 4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Date: Thu, 30 Mar 2023 21:42:15 +0100 [thread overview] Message-ID: <20230330204217.47666-5-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw) In-Reply-To: <20230330204217.47666-1-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Add DT binding documentation for L2 cache controller found on RZ/Five SoC. The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. The AX45MP core has an L2 cache controller, this patch describes the L2 cache block. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> --- v6 -> v7 * No Change v5 -> v6 * Included RB tag from Rob v4 -> v5 * Dropped L2 cache configuration properties * Dropped PMA configuration properties * Ordered the required list to match the properties list RFC v3 -> v4 * Dropped l2 cache configuration parameters * s/larger/large * Added minItems/maxItems for andestech,pma-regions --- .../cache/andestech,ax45mp-cache.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml new file mode 100644 index 000000000000..9ab5f0c435d4 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andestech AX45MP L2 Cache Controller + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: + A level-2 cache (L2C) is used to improve the system performance by providing + a large amount of cache line entries and reasonable access delays. The L2C + is shared between cores, and a non-inclusive non-exclusive policy is used. + +select: + properties: + compatible: + contains: + enum: + - andestech,ax45mp-cache + + required: + - compatible + +properties: + compatible: + items: + - const: andestech,ax45mp-cache + - const: cache + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cache-line-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + enum: [131072, 262144, 524288, 1048576, 2097152] + + cache-unified: true + + next-level-cache: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - cache-line-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + cache-controller@2010000 { + compatible = "andestech,ax45mp-cache", "cache"; + reg = <0x13400000 0x100000>; + interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <262144>; + cache-unified; + }; -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-03-30 20:43 UTC|newest] Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-30 20:42 [PATCH v7 0/6] RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP Prabhakar 2023-03-30 20:42 ` Prabhakar 2023-03-30 20:42 ` [PATCH v7 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management Prabhakar 2023-03-30 20:42 ` Prabhakar 2023-03-30 21:34 ` Arnd Bergmann 2023-03-30 21:34 ` Arnd Bergmann 2023-03-31 7:54 ` Conor Dooley 2023-03-31 7:54 ` Conor Dooley 2023-03-31 7:58 ` Arnd Bergmann 2023-03-31 7:58 ` Arnd Bergmann 2023-03-31 10:37 ` Lad, Prabhakar 2023-03-31 10:37 ` Lad, Prabhakar 2023-03-31 10:44 ` Arnd Bergmann 2023-03-31 10:44 ` Arnd Bergmann 2023-03-31 12:11 ` Lad, Prabhakar 2023-03-31 12:11 ` Lad, Prabhakar 2023-04-03 17:00 ` Lad, Prabhakar 2023-04-03 17:00 ` Lad, Prabhakar 2023-03-31 10:55 ` Conor Dooley 2023-03-31 10:55 ` Conor Dooley 2023-03-31 11:36 ` Arnd Bergmann 2023-03-31 11:36 ` Arnd Bergmann 2023-03-31 7:31 ` Geert Uytterhoeven 2023-03-31 7:31 ` Geert Uytterhoeven 2023-03-31 10:45 ` Lad, Prabhakar 2023-03-31 10:45 ` Lad, Prabhakar 2023-03-31 12:24 ` Conor Dooley 2023-03-31 12:24 ` Conor Dooley 2023-04-03 18:23 ` Lad, Prabhakar 2023-04-03 18:23 ` Lad, Prabhakar 2023-04-03 18:31 ` Conor Dooley 2023-04-03 18:31 ` Conor Dooley 2023-04-04 5:29 ` Christoph Hellwig 2023-04-04 5:29 ` Christoph Hellwig 2023-04-04 6:24 ` Biju Das 2023-04-04 6:24 ` Biju Das 2023-04-04 15:42 ` Christoph Hellwig 2023-04-04 15:42 ` Christoph Hellwig 2023-04-05 6:08 ` Biju Das 2023-04-05 6:08 ` Biju Das 2023-04-07 0:03 ` Andrea Parri 2023-04-07 0:03 ` Andrea Parri 2023-04-07 5:33 ` Christoph Hellwig 2023-04-07 5:33 ` Christoph Hellwig 2023-04-04 6:50 ` Arnd Bergmann 2023-04-04 6:50 ` Arnd Bergmann 2023-04-04 6:59 ` Conor Dooley 2023-04-04 6:59 ` Conor Dooley 2023-04-06 18:59 ` Lad, Prabhakar 2023-04-06 18:59 ` Lad, Prabhakar 2023-03-30 20:42 ` [PATCH v7 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar 2023-03-30 20:42 ` Prabhakar 2023-03-30 20:42 ` [PATCH v7 3/6] riscv: errata: Add Andes alternative ports Prabhakar 2023-03-30 20:42 ` Prabhakar 2023-03-30 20:42 ` Prabhakar [this message] 2023-03-30 20:42 ` [PATCH v7 4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar 2023-03-31 10:21 ` Conor Dooley 2023-03-31 10:21 ` Conor Dooley 2023-03-31 10:47 ` Lad, Prabhakar 2023-03-31 10:47 ` Lad, Prabhakar 2023-03-30 20:42 ` [PATCH v7 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core Prabhakar 2023-03-30 20:42 ` Prabhakar 2023-03-31 12:45 ` Conor Dooley 2023-03-31 12:45 ` Conor Dooley 2023-03-31 20:17 ` Lad, Prabhakar 2023-03-31 20:17 ` Lad, Prabhakar 2023-03-30 20:42 ` [PATCH v7 6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Prabhakar 2023-03-30 20:42 ` Prabhakar 2023-03-31 7:37 ` Geert Uytterhoeven 2023-03-31 7:37 ` Geert Uytterhoeven 2023-03-31 7:37 ` Geert Uytterhoeven 2023-03-31 7:37 ` Geert Uytterhoeven 2023-03-31 18:05 ` [PATCH v7 0/6] RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP Conor Dooley 2023-03-31 18:05 ` Conor Dooley 2023-03-31 20:09 ` Lad, Prabhakar 2023-03-31 20:09 ` Lad, Prabhakar 2023-03-31 20:15 ` Conor Dooley 2023-03-31 20:15 ` Conor Dooley 2023-04-01 1:47 ` Icenowy Zheng 2023-04-01 1:47 ` Icenowy Zheng
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230330204217.47666-5-prabhakar.mahadev-lad.rj@bp.renesas.com \ --to=prabhakar.csengg@gmail.com \ --cc=ajones@ventanamicro.com \ --cc=aou@eecs.berkeley.edu \ --cc=arnd@arndb.de \ --cc=biju.das.jz@bp.renesas.com \ --cc=conor.dooley@microchip.com \ --cc=devicetree@vger.kernel.org \ --cc=geert+renesas@glider.be \ --cc=guoren@kernel.org \ --cc=heiko@sntech.de \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-renesas-soc@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=prabhakar.mahadev-lad.rj@bp.renesas.com \ --cc=robh+dt@kernel.org \ --cc=robh@kernel.org \ --cc=samuel@sholland.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.