From: Garmin.Chang <Garmin.Chang@mediatek.com> To: Matthias Brugger <matthias.bgg@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Richard Cochran <richardcochran@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: <Project_Global_Chrome_Upstream_Group@mediatek.com>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>, <netdev@vger.kernel.org>, Garmin.Chang <Garmin.Chang@mediatek.com> Subject: [PATCH v7 11/19] clk: mediatek: Add MT8188 vdecsys clock support Date: Fri, 31 Mar 2023 16:21:23 +0800 [thread overview] Message-ID: <20230331082131.12517-12-Garmin.Chang@mediatek.com> (raw) In-Reply-To: <20230331082131.12517-1-Garmin.Chang@mediatek.com> Add MT8188 vdec clock controllers which provide clock gate control for video decoder. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> --- drivers/clk/mediatek/Kconfig | 7 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8188-vdec.c | 92 ++++++++++++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8188-vdec.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index d1239c7ac9f4..8470684daa46 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -720,6 +720,13 @@ config COMMON_CLK_MT8188_MFGCFG help This driver supports MediaTek MT8188 mfgcfg clocks. +config COMMON_CLK_MT8188_VDECSYS + tristate "Clock driver for MediaTek MT8188 vdecsys" + depends on COMMON_CLK_MT8188_VPPSYS + default COMMON_CLK_MT8188_VPPSYS + help + This driver supports MediaTek MT8188 vdecsys and vdecsys_soc clocks. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 16ba3c97c4e8..b63d38804809 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -106,6 +106,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_CAMSYS) += clk-mt8188-cam.o clk-mt8188-ccu.o obj-$(CONFIG_COMMON_CLK_MT8188_IMGSYS) += clk-mt8188-img.o obj-$(CONFIG_COMMON_CLK_MT8188_IPESYS) += clk-mt8188-ipe.o obj-$(CONFIG_COMMON_CLK_MT8188_MFGCFG) += clk-mt8188-mfg.o +obj-$(CONFIG_COMMON_CLK_MT8188_VDECSYS) += clk-mt8188-vdec.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8188-vdec.c b/drivers/clk/mediatek/clk-mt8188-vdec.c new file mode 100644 index 000000000000..8c3d76531753 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-vdec.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs vdec0_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x4, + .sta_ofs = 0x0, +}; + +static const struct mtk_gate_regs vdec1_cg_regs = { + .set_ofs = 0x200, + .clr_ofs = 0x204, + .sta_ofs = 0x200, +}; + +static const struct mtk_gate_regs vdec2_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0xc, + .sta_ofs = 0x8, +}; + +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_VDEC2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +static const struct mtk_gate vdec1_clks[] = { + /* VDEC1_0 */ + GATE_VDEC0(CLK_VDEC1_SOC_VDEC, "vdec1_soc_vdec", "top_vdec", 0), + GATE_VDEC0(CLK_VDEC1_SOC_VDEC_ACTIVE, "vdec1_soc_vdec_active", "top_vdec", 4), + GATE_VDEC0(CLK_VDEC1_SOC_VDEC_ENG, "vdec1_soc_vdec_eng", "top_vdec", 8), + /* VDEC1_1 */ + GATE_VDEC1(CLK_VDEC1_SOC_LAT, "vdec1_soc_lat", "top_vdec", 0), + GATE_VDEC1(CLK_VDEC1_SOC_LAT_ACTIVE, "vdec1_soc_lat_active", "top_vdec", 4), + GATE_VDEC1(CLK_VDEC1_SOC_LAT_ENG, "vdec1_soc_lat_eng", "top_vdec", 8), + /* VDEC1_2 */ + GATE_VDEC2(CLK_VDEC1_SOC_LARB1, "vdec1_soc_larb1", "top_vdec", 0), +}; + +static const struct mtk_gate vdec2_clks[] = { + /* VDEC2_0 */ + GATE_VDEC0(CLK_VDEC2_VDEC, "vdec2_vdec", "top_vdec", 0), + GATE_VDEC0(CLK_VDEC2_VDEC_ACTIVE, "vdec2_vdec_active", "top_vdec", 4), + GATE_VDEC0(CLK_VDEC2_VDEC_ENG, "vdec2_vdec_eng", "top_vdec", 8), + /* VDEC2_1 */ + GATE_VDEC1(CLK_VDEC2_LAT, "vdec2_lat", "top_vdec", 0), + /* VDEC2_2 */ + GATE_VDEC2(CLK_VDEC2_LARB1, "vdec2_larb1", "top_vdec", 0), +}; + +static const struct mtk_clk_desc vdec1_desc = { + .clks = vdec1_clks, + .num_clks = ARRAY_SIZE(vdec1_clks), +}; + +static const struct mtk_clk_desc vdec2_desc = { + .clks = vdec2_clks, + .num_clks = ARRAY_SIZE(vdec2_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_vdec[] = { + { .compatible = "mediatek,mt8188-vdecsys-soc", .data = &vdec1_desc }, + { .compatible = "mediatek,mt8188-vdecsys", .data = &vdec2_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_vdec); + +static struct platform_driver clk_mt8188_vdec_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-vdec", + .of_match_table = of_match_clk_mt8188_vdec, + }, +}; + +module_platform_driver(clk_mt8188_vdec_drv); +MODULE_LICENSE("GPL"); -- 2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Garmin.Chang <Garmin.Chang@mediatek.com> To: Matthias Brugger <matthias.bgg@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Richard Cochran <richardcochran@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: <Project_Global_Chrome_Upstream_Group@mediatek.com>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>, <netdev@vger.kernel.org>, Garmin.Chang <Garmin.Chang@mediatek.com> Subject: [PATCH v7 11/19] clk: mediatek: Add MT8188 vdecsys clock support Date: Fri, 31 Mar 2023 16:21:23 +0800 [thread overview] Message-ID: <20230331082131.12517-12-Garmin.Chang@mediatek.com> (raw) In-Reply-To: <20230331082131.12517-1-Garmin.Chang@mediatek.com> Add MT8188 vdec clock controllers which provide clock gate control for video decoder. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> --- drivers/clk/mediatek/Kconfig | 7 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8188-vdec.c | 92 ++++++++++++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8188-vdec.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index d1239c7ac9f4..8470684daa46 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -720,6 +720,13 @@ config COMMON_CLK_MT8188_MFGCFG help This driver supports MediaTek MT8188 mfgcfg clocks. +config COMMON_CLK_MT8188_VDECSYS + tristate "Clock driver for MediaTek MT8188 vdecsys" + depends on COMMON_CLK_MT8188_VPPSYS + default COMMON_CLK_MT8188_VPPSYS + help + This driver supports MediaTek MT8188 vdecsys and vdecsys_soc clocks. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 16ba3c97c4e8..b63d38804809 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -106,6 +106,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_CAMSYS) += clk-mt8188-cam.o clk-mt8188-ccu.o obj-$(CONFIG_COMMON_CLK_MT8188_IMGSYS) += clk-mt8188-img.o obj-$(CONFIG_COMMON_CLK_MT8188_IPESYS) += clk-mt8188-ipe.o obj-$(CONFIG_COMMON_CLK_MT8188_MFGCFG) += clk-mt8188-mfg.o +obj-$(CONFIG_COMMON_CLK_MT8188_VDECSYS) += clk-mt8188-vdec.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8188-vdec.c b/drivers/clk/mediatek/clk-mt8188-vdec.c new file mode 100644 index 000000000000..8c3d76531753 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-vdec.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs vdec0_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x4, + .sta_ofs = 0x0, +}; + +static const struct mtk_gate_regs vdec1_cg_regs = { + .set_ofs = 0x200, + .clr_ofs = 0x204, + .sta_ofs = 0x200, +}; + +static const struct mtk_gate_regs vdec2_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0xc, + .sta_ofs = 0x8, +}; + +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_VDEC2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +static const struct mtk_gate vdec1_clks[] = { + /* VDEC1_0 */ + GATE_VDEC0(CLK_VDEC1_SOC_VDEC, "vdec1_soc_vdec", "top_vdec", 0), + GATE_VDEC0(CLK_VDEC1_SOC_VDEC_ACTIVE, "vdec1_soc_vdec_active", "top_vdec", 4), + GATE_VDEC0(CLK_VDEC1_SOC_VDEC_ENG, "vdec1_soc_vdec_eng", "top_vdec", 8), + /* VDEC1_1 */ + GATE_VDEC1(CLK_VDEC1_SOC_LAT, "vdec1_soc_lat", "top_vdec", 0), + GATE_VDEC1(CLK_VDEC1_SOC_LAT_ACTIVE, "vdec1_soc_lat_active", "top_vdec", 4), + GATE_VDEC1(CLK_VDEC1_SOC_LAT_ENG, "vdec1_soc_lat_eng", "top_vdec", 8), + /* VDEC1_2 */ + GATE_VDEC2(CLK_VDEC1_SOC_LARB1, "vdec1_soc_larb1", "top_vdec", 0), +}; + +static const struct mtk_gate vdec2_clks[] = { + /* VDEC2_0 */ + GATE_VDEC0(CLK_VDEC2_VDEC, "vdec2_vdec", "top_vdec", 0), + GATE_VDEC0(CLK_VDEC2_VDEC_ACTIVE, "vdec2_vdec_active", "top_vdec", 4), + GATE_VDEC0(CLK_VDEC2_VDEC_ENG, "vdec2_vdec_eng", "top_vdec", 8), + /* VDEC2_1 */ + GATE_VDEC1(CLK_VDEC2_LAT, "vdec2_lat", "top_vdec", 0), + /* VDEC2_2 */ + GATE_VDEC2(CLK_VDEC2_LARB1, "vdec2_larb1", "top_vdec", 0), +}; + +static const struct mtk_clk_desc vdec1_desc = { + .clks = vdec1_clks, + .num_clks = ARRAY_SIZE(vdec1_clks), +}; + +static const struct mtk_clk_desc vdec2_desc = { + .clks = vdec2_clks, + .num_clks = ARRAY_SIZE(vdec2_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_vdec[] = { + { .compatible = "mediatek,mt8188-vdecsys-soc", .data = &vdec1_desc }, + { .compatible = "mediatek,mt8188-vdecsys", .data = &vdec2_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_vdec); + +static struct platform_driver clk_mt8188_vdec_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-vdec", + .of_match_table = of_match_clk_mt8188_vdec, + }, +}; + +module_platform_driver(clk_mt8188_vdec_drv); +MODULE_LICENSE("GPL"); -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-03-31 8:43 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-31 8:21 [PATCH v7 00/19] MediaTek MT8188 clock support Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 8:21 ` [PATCH v7 01/19] dt-bindings: clock: mediatek: Add new MT8188 clock Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 8:21 ` [PATCH v7 02/19] clk: mediatek: Add MT8188 apmixedsys clock support Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 03/19] clk: mediatek: Add MT8188 topckgen " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 04/19] clk: mediatek: Add MT8188 peripheral " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 05/19] clk: mediatek: Add MT8188 infrastructure " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 06/19] clk: mediatek: Add MT8188 camsys " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 10:28 ` Garmin Chang (張家銘) 2023-03-31 10:28 ` Garmin Chang (張家銘) 2023-03-31 8:21 ` [PATCH v7 07/19] clk: mediatek: Add MT8188 ccusys " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 08/19] clk: mediatek: Add MT8188 imgsys " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 09/19] clk: mediatek: Add MT8188 ipesys " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 10/19] clk: mediatek: Add MT8188 mfgcfg " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` Garmin.Chang [this message] 2023-03-31 8:21 ` [PATCH v7 11/19] clk: mediatek: Add MT8188 vdecsys " Garmin.Chang 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 12/19] clk: mediatek: Add MT8188 vdosys0 " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 13/19] clk: mediatek: Add MT8188 vdosys1 " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 14/19] clk: mediatek: Add MT8188 vencsys " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 9:54 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 15/19] clk: mediatek: Add MT8188 vppsys0 " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 16/19] clk: mediatek: Add MT8188 vppsys1 " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 17/19] clk: mediatek: Add MT8188 wpesys " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 18/19] clk: mediatek: Add MT8188 imp i2c wrapper " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 8:21 ` [PATCH v7 19/19] clk: mediatek: Add MT8188 adsp " Garmin.Chang 2023-03-31 8:21 ` Garmin.Chang 2023-03-31 9:53 ` AngeloGioacchino Del Regno 2023-03-31 9:53 ` AngeloGioacchino Del Regno
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