From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com> To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-imx@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Peng Fan <peng.fan@nxp.com> Subject: [PATCH V3 2/7] clk: imx: fracn-gppll: disable hardware select control Date: Mon, 3 Apr 2023 17:52:55 +0800 [thread overview] Message-ID: <20230403095300.3386988-3-peng.fan@oss.nxp.com> (raw) In-Reply-To: <20230403095300.3386988-1-peng.fan@oss.nxp.com> From: Peng Fan <peng.fan@nxp.com> When programming PLL, should disable Hardware control select to make PLL controlled by register, not hardware inputs through OSCPLL. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Peng Fan <peng.fan@nxp.com> --- drivers/clk/imx/clk-fracn-gppll.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index ec50c41e2a4c..f6674110a88e 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -15,6 +15,7 @@ #include "clk.h" #define PLL_CTRL 0x0 +#define HW_CTRL_SEL BIT(16) #define CLKMUX_BYPASS BIT(2) #define CLKMUX_EN BIT(1) #define POWERUP_MASK BIT(0) @@ -193,6 +194,11 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate, rate = imx_get_pll_settings(pll, drate); + /* Hardware control select disable. PLL is control by register */ + tmp = readl_relaxed(pll->base + PLL_CTRL); + tmp &= ~HW_CTRL_SEL; + writel_relaxed(tmp, pll->base + PLL_CTRL); + /* Disable output */ tmp = readl_relaxed(pll->base + PLL_CTRL); tmp &= ~CLKMUX_EN; -- 2.37.1
WARNING: multiple messages have this Message-ID (diff)
From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com> To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-imx@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Peng Fan <peng.fan@nxp.com> Subject: [PATCH V3 2/7] clk: imx: fracn-gppll: disable hardware select control Date: Mon, 3 Apr 2023 17:52:55 +0800 [thread overview] Message-ID: <20230403095300.3386988-3-peng.fan@oss.nxp.com> (raw) In-Reply-To: <20230403095300.3386988-1-peng.fan@oss.nxp.com> From: Peng Fan <peng.fan@nxp.com> When programming PLL, should disable Hardware control select to make PLL controlled by register, not hardware inputs through OSCPLL. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Peng Fan <peng.fan@nxp.com> --- drivers/clk/imx/clk-fracn-gppll.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index ec50c41e2a4c..f6674110a88e 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -15,6 +15,7 @@ #include "clk.h" #define PLL_CTRL 0x0 +#define HW_CTRL_SEL BIT(16) #define CLKMUX_BYPASS BIT(2) #define CLKMUX_EN BIT(1) #define POWERUP_MASK BIT(0) @@ -193,6 +194,11 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate, rate = imx_get_pll_settings(pll, drate); + /* Hardware control select disable. PLL is control by register */ + tmp = readl_relaxed(pll->base + PLL_CTRL); + tmp &= ~HW_CTRL_SEL; + writel_relaxed(tmp, pll->base + PLL_CTRL); + /* Disable output */ tmp = readl_relaxed(pll->base + PLL_CTRL); tmp &= ~CLKMUX_EN; -- 2.37.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-04-03 9:49 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-03 9:52 [PATCH V3 0/7] clk: imx: imx93: fix and update Peng Fan (OSS) 2023-04-03 9:52 ` Peng Fan (OSS) 2023-04-03 9:52 ` [PATCH V3 1/7] clk: imx: fracn-gppll: fix the rate table Peng Fan (OSS) 2023-04-03 9:52 ` Peng Fan (OSS) 2023-04-09 13:44 ` Abel Vesa 2023-04-09 13:44 ` Abel Vesa 2023-04-03 9:52 ` Peng Fan (OSS) [this message] 2023-04-03 9:52 ` [PATCH V3 2/7] clk: imx: fracn-gppll: disable hardware select control Peng Fan (OSS) 2023-04-09 13:44 ` Abel Vesa 2023-04-09 13:44 ` Abel Vesa 2023-04-03 9:52 ` [PATCH V3 3/7] clk: imx: fracn-gppll: support integer pll Peng Fan (OSS) 2023-04-03 9:52 ` Peng Fan (OSS) 2023-04-09 13:45 ` Abel Vesa 2023-04-09 13:45 ` Abel Vesa 2023-04-03 9:52 ` [PATCH V3 4/7] clk: imx: fracn-gppll: Add 300MHz freq support for imx9 Peng Fan (OSS) 2023-04-03 9:52 ` Peng Fan (OSS) 2023-04-09 13:46 ` Abel Vesa 2023-04-09 13:46 ` Abel Vesa 2023-04-03 9:52 ` [PATCH V3 5/7] clk: imx: imx93: add mcore_booted module paratemter Peng Fan (OSS) 2023-04-03 9:52 ` Peng Fan (OSS) 2023-04-09 13:46 ` Abel Vesa 2023-04-09 13:46 ` Abel Vesa 2023-04-03 9:52 ` [PATCH V3 6/7] dt-bindings: clock: imx93: add NIC, A55 and ARM PLL CLK Peng Fan (OSS) 2023-04-03 9:52 ` Peng Fan (OSS) 2023-04-03 10:32 ` Krzysztof Kozlowski 2023-04-03 10:32 ` Krzysztof Kozlowski 2023-04-03 9:53 ` [PATCH V3 7/7] clk: imx: imx93: Add nic and A55 clk Peng Fan (OSS) 2023-04-03 9:53 ` Peng Fan (OSS) 2023-04-09 13:47 ` Abel Vesa 2023-04-09 13:47 ` Abel Vesa 2023-04-09 13:53 ` [PATCH V3 0/7] clk: imx: imx93: fix and update Abel Vesa 2023-04-09 13:53 ` Abel Vesa
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