From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: "Atish Patra" <atishp@rivosinc.com>, "Alexandre Ghiti" <alex@ghiti.fr>, "Andrew Jones" <ajones@ventanamicro.com>, "Andrew Morton" <akpm@linux-foundation.org>, "Anup Patel" <anup@brainfault.org>, "Atish Patra" <atishp@atishpatra.org>, "Björn Töpel" <bjorn@rivosinc.com>, "Suzuki K Poulose" <suzuki.poulose@arm.com>, "Will Deacon" <will@kernel.org>, "Marc Zyngier" <maz@kernel.org>, "Sean Christopherson" <seanjc@google.com>, linux-coco@lists.linux.dev, "Dylan Reid" <dylan@rivosinc.com>, abrestic@rivosinc.com, "Samuel Ortiz" <sameo@rivosinc.com>, "Christoph Hellwig" <hch@infradead.org>, "Conor Dooley" <conor.dooley@microchip.com>, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "Guo Ren" <guoren@kernel.org>, "Heiko Stuebner" <heiko@sntech.de>, "Jiri Slaby" <jirislaby@kernel.org>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, "Mayuresh Chitale" <mchitale@ventanamicro.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Rajnesh Kanwal" <rkanwal@rivosinc.com>, "Uladzislau Rezki" <urezki@gmail.com> Subject: [RFC 15/48] RISC-V: KVM: Add a helper function to trigger fence ops Date: Wed, 19 Apr 2023 15:16:43 -0700 [thread overview] Message-ID: <20230419221716.3603068-16-atishp@rivosinc.com> (raw) In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> When Cove is enabled in RISC-V, the TLB shootdown happens in co-ordination with TSM. The host must not issue hfence directly. It relies on TSM to do that instead. It just needs to initiate the process and make sure that all the running vcpus exit the guest mode. As a result, it traps to TSM and TSM issues hfence on behalf of the host. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/kvm_cove.h | 2 ++ arch/riscv/kvm/cove.c | 36 +++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/riscv/include/asm/kvm_cove.h b/arch/riscv/include/asm/kvm_cove.h index 4ea1df1..fc8633d 100644 --- a/arch/riscv/include/asm/kvm_cove.h +++ b/arch/riscv/include/asm/kvm_cove.h @@ -130,6 +130,8 @@ void kvm_riscv_cove_vcpu_switchto(struct kvm_vcpu *vcpu, struct kvm_cpu_trap *tr int kvm_riscv_cove_vm_measure_pages(struct kvm *kvm, struct kvm_riscv_cove_measure_region *mr); int kvm_riscv_cove_vm_add_memreg(struct kvm *kvm, unsigned long gpa, unsigned long size); int kvm_riscv_cove_gstage_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hva); +/* Fence related function */ +int kvm_riscv_cove_tvm_fence(struct kvm_vcpu *vcpu); #else static inline bool kvm_riscv_cove_enabled(void) {return false; }; static inline int kvm_riscv_cove_init(void) { return -1; } diff --git a/arch/riscv/kvm/cove.c b/arch/riscv/kvm/cove.c index 5b4d9ba..4efcae3 100644 --- a/arch/riscv/kvm/cove.c +++ b/arch/riscv/kvm/cove.c @@ -78,6 +78,42 @@ static int kvm_riscv_cove_fence(void) return rc; } +int kvm_riscv_cove_tvm_fence(struct kvm_vcpu *vcpu) +{ + struct kvm *kvm = vcpu->kvm; + struct kvm_cove_tvm_context *tvmc = kvm->arch.tvmc; + DECLARE_BITMAP(vcpu_mask, KVM_MAX_VCPUS); + unsigned long i; + struct kvm_vcpu *temp_vcpu; + int ret; + + if (!tvmc) + return -EINVAL; + + spin_lock(&tvmc->tvm_fence_lock); + ret = sbi_covh_tvm_initiate_fence(tvmc->tvm_guest_id); + if (ret) { + spin_unlock(&tvmc->tvm_fence_lock); + return ret; + } + + bitmap_clear(vcpu_mask, 0, KVM_MAX_VCPUS); + kvm_for_each_vcpu(i, temp_vcpu, kvm) { + if (temp_vcpu != vcpu) + bitmap_set(vcpu_mask, i, 1); + } + + /* + * The host just needs to make sure that the running vcpus exit the + * guest mode and traps into TSM so that it can issue hfence. + */ + kvm_make_vcpus_request_mask(kvm, KVM_REQ_OUTSIDE_GUEST_MODE, vcpu_mask); + spin_unlock(&tvmc->tvm_fence_lock); + + return 0; +} + + static int cove_convert_pages(unsigned long phys_addr, unsigned long npages, bool fence) { int rc; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: "Atish Patra" <atishp@rivosinc.com>, "Alexandre Ghiti" <alex@ghiti.fr>, "Andrew Jones" <ajones@ventanamicro.com>, "Andrew Morton" <akpm@linux-foundation.org>, "Anup Patel" <anup@brainfault.org>, "Atish Patra" <atishp@atishpatra.org>, "Björn Töpel" <bjorn@rivosinc.com>, "Suzuki K Poulose" <suzuki.poulose@arm.com>, "Will Deacon" <will@kernel.org>, "Marc Zyngier" <maz@kernel.org>, "Sean Christopherson" <seanjc@google.com>, linux-coco@lists.linux.dev, "Dylan Reid" <dylan@rivosinc.com>, abrestic@rivosinc.com, "Samuel Ortiz" <sameo@rivosinc.com>, "Christoph Hellwig" <hch@infradead.org>, "Conor Dooley" <conor.dooley@microchip.com>, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "Guo Ren" <guoren@kernel.org>, "Heiko Stuebner" <heiko@sntech.de>, "Jiri Slaby" <jirislaby@kernel.org>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, "Mayuresh Chitale" <mchitale@ventanamicro.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Rajnesh Kanwal" <rkanwal@rivosinc.com>, "Uladzislau Rezki" <urezki@gmail.com> Subject: [RFC 15/48] RISC-V: KVM: Add a helper function to trigger fence ops Date: Wed, 19 Apr 2023 15:16:43 -0700 [thread overview] Message-ID: <20230419221716.3603068-16-atishp@rivosinc.com> (raw) In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> When Cove is enabled in RISC-V, the TLB shootdown happens in co-ordination with TSM. The host must not issue hfence directly. It relies on TSM to do that instead. It just needs to initiate the process and make sure that all the running vcpus exit the guest mode. As a result, it traps to TSM and TSM issues hfence on behalf of the host. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/kvm_cove.h | 2 ++ arch/riscv/kvm/cove.c | 36 +++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/riscv/include/asm/kvm_cove.h b/arch/riscv/include/asm/kvm_cove.h index 4ea1df1..fc8633d 100644 --- a/arch/riscv/include/asm/kvm_cove.h +++ b/arch/riscv/include/asm/kvm_cove.h @@ -130,6 +130,8 @@ void kvm_riscv_cove_vcpu_switchto(struct kvm_vcpu *vcpu, struct kvm_cpu_trap *tr int kvm_riscv_cove_vm_measure_pages(struct kvm *kvm, struct kvm_riscv_cove_measure_region *mr); int kvm_riscv_cove_vm_add_memreg(struct kvm *kvm, unsigned long gpa, unsigned long size); int kvm_riscv_cove_gstage_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hva); +/* Fence related function */ +int kvm_riscv_cove_tvm_fence(struct kvm_vcpu *vcpu); #else static inline bool kvm_riscv_cove_enabled(void) {return false; }; static inline int kvm_riscv_cove_init(void) { return -1; } diff --git a/arch/riscv/kvm/cove.c b/arch/riscv/kvm/cove.c index 5b4d9ba..4efcae3 100644 --- a/arch/riscv/kvm/cove.c +++ b/arch/riscv/kvm/cove.c @@ -78,6 +78,42 @@ static int kvm_riscv_cove_fence(void) return rc; } +int kvm_riscv_cove_tvm_fence(struct kvm_vcpu *vcpu) +{ + struct kvm *kvm = vcpu->kvm; + struct kvm_cove_tvm_context *tvmc = kvm->arch.tvmc; + DECLARE_BITMAP(vcpu_mask, KVM_MAX_VCPUS); + unsigned long i; + struct kvm_vcpu *temp_vcpu; + int ret; + + if (!tvmc) + return -EINVAL; + + spin_lock(&tvmc->tvm_fence_lock); + ret = sbi_covh_tvm_initiate_fence(tvmc->tvm_guest_id); + if (ret) { + spin_unlock(&tvmc->tvm_fence_lock); + return ret; + } + + bitmap_clear(vcpu_mask, 0, KVM_MAX_VCPUS); + kvm_for_each_vcpu(i, temp_vcpu, kvm) { + if (temp_vcpu != vcpu) + bitmap_set(vcpu_mask, i, 1); + } + + /* + * The host just needs to make sure that the running vcpus exit the + * guest mode and traps into TSM so that it can issue hfence. + */ + kvm_make_vcpus_request_mask(kvm, KVM_REQ_OUTSIDE_GUEST_MODE, vcpu_mask); + spin_unlock(&tvmc->tvm_fence_lock); + + return 0; +} + + static int cove_convert_pages(unsigned long phys_addr, unsigned long npages, bool fence) { int rc; -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-04-19 22:18 UTC|newest] Thread overview: 134+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-19 22:16 [RFC 00/48] RISC-V CoVE support Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 01/48] mm/vmalloc: Introduce arch hooks to notify ioremap/unmap changes Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-20 19:42 ` Lorenzo Stoakes 2023-04-20 19:42 ` Lorenzo Stoakes 2023-04-20 22:01 ` Atish Kumar Patra 2023-04-20 22:01 ` Atish Kumar Patra 2023-04-19 22:16 ` [RFC 02/48] RISC-V: KVM: Improve KVM error reporting to the user space Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 03/48] RISC-V: KVM: Invoke aia_update with preempt disabled/irq enabled Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 04/48] RISC-V: KVM: Add a helper function to get pgd size Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 05/48] RISC-V: Add COVH SBI extensions definitions Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 06/48] RISC-V: KVM: Implement COVH SBI extension Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 07/48] RISC-V: KVM: Add a barebone CoVE implementation Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 08/48] RISC-V: KVM: Add UABI to support static memory region attestation Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 09/48] RISC-V: KVM: Add CoVE related nacl helpers Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 10/48] RISC-V: KVM: Implement static memory region measurement Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-20 15:17 ` Sean Christopherson 2023-04-20 15:17 ` Sean Christopherson 2023-04-21 18:50 ` Atish Kumar Patra 2023-04-21 18:50 ` Atish Kumar Patra 2023-04-19 22:16 ` [RFC 11/48] RISC-V: KVM: Use the new VM IOCTL for measuring pages Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 12/48] RISC-V: KVM: Exit to the user space for trap redirection Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 13/48] RISC-V: KVM: Return early for gstage modifications Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 14/48] RISC-V: KVM: Skip dirty logging updates for TVM Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` Atish Patra [this message] 2023-04-19 22:16 ` [RFC 15/48] RISC-V: KVM: Add a helper function to trigger fence ops Atish Patra 2023-04-19 22:16 ` [RFC 16/48] RISC-V: KVM: Skip most VCPU requests for TVMs Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 17/48] RISC-V : KVM: Skip vmid/hgatp management " Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 18/48] RISC-V: KVM: Skip TLB " Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 19/48] RISC-V: KVM: Register memory regions as confidential " Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 20/48] RISC-V: KVM: Add gstage mapping " Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 21/48] RISC-V: KVM: Handle SBI call forward from the TSM Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 22/48] RISC-V: KVM: Implement vcpu load/put functions for CoVE guests Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 23/48] RISC-V: KVM: Wireup TVM world switch Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 24/48] RISC-V: KVM: Update timer functionality for TVMs Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 25/48] RISC-V: KVM: Skip HVIP update " Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 26/48] RISC-V: Add COVI extension definitions Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 27/48] RISC-V: KVM: Implement COVI SBI extension Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 28/48] RISC-V: KVM: Add interrupt management functions for TVM Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 29/48] RISC-V: KVM: Skip AIA CSR updates for TVMs Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 30/48] RISC-V: KVM: Perform limited operations in hardware enable/disable Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 31/48] RISC-V: KVM: Indicate no support user space emulated IRQCHIP Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:17 ` [RFC 32/48] RISC-V: KVM: Add AIA support for TVMs Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 33/48] RISC-V: KVM: Hookup TVM VCPU init/destroy Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 34/48] RISC-V: KVM: Initialize CoVE Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 35/48] RISC-V: KVM: Add TVM init/destroy calls Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 36/48] RISC-V: KVM: Read/write gprs from/to shmem in case of TVM VCPU Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 37/48] RISC-V: Add COVG SBI extension definitions Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 38/48] RISC-V: Add CoVE guest config and helper functions Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 39/48] RISC-V: Implement COVG SBI extension Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 40/48] RISC-V: COVE: Add COVH invalidate, validate, promote, demote and remove APIs Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 41/48] RISC-V: KVM: Add host side support to handle COVG SBI calls Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 42/48] RISC-V: Allow host to inject any ext interrupt id to a CoVE guest Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 43/48] RISC-V: Add base memory encryption functions Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 44/48] RISC-V: Add cc_platform_has() for RISC-V for CoVE Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 45/48] RISC-V: ioremap: Implement for arch specific ioremap hooks Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-20 22:15 ` Dave Hansen 2023-04-20 22:15 ` Dave Hansen 2023-04-21 19:24 ` Atish Kumar Patra 2023-04-21 19:24 ` Atish Kumar Patra 2023-04-24 13:48 ` Dave Hansen 2023-04-24 13:48 ` Dave Hansen 2023-04-25 8:00 ` Atish Kumar Patra 2023-04-25 8:00 ` Atish Kumar Patra 2023-04-25 13:10 ` Dave Hansen 2023-04-25 13:10 ` Dave Hansen 2023-04-26 8:02 ` Atish Kumar Patra 2023-04-26 8:02 ` Atish Kumar Patra 2023-04-26 10:30 ` Anup Patel 2023-04-26 10:30 ` Anup Patel 2023-04-26 13:55 ` Andrew Bresticker 2023-04-26 13:55 ` Andrew Bresticker 2023-04-19 22:17 ` [RFC 46/48] riscv/virtio: Have CoVE guests enforce restricted virtio memory access Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 47/48] RISC-V: Add shared bounce buffer to support DBCN for CoVE Guest Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 48/48] drivers/hvc: sbi: Disable HVC console for TVMs Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:58 ` [RFC 00/48] RISC-V CoVE support Atish Patra 2023-04-19 22:58 ` Atish Patra 2023-04-20 16:30 ` Sean Christopherson 2023-04-20 16:30 ` Sean Christopherson 2023-04-20 19:13 ` Atish Kumar Patra 2023-04-20 19:13 ` Atish Kumar Patra 2023-04-20 20:21 ` Sean Christopherson 2023-04-20 20:21 ` Sean Christopherson 2023-04-21 15:35 ` Michael Roth 2023-04-21 15:35 ` Michael Roth 2023-04-24 12:23 ` Christophe de Dinechin 2023-04-24 12:23 ` Christophe de Dinechin
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