From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: "Atish Patra" <atishp@rivosinc.com>, "Alexandre Ghiti" <alex@ghiti.fr>, "Andrew Jones" <ajones@ventanamicro.com>, "Andrew Morton" <akpm@linux-foundation.org>, "Anup Patel" <anup@brainfault.org>, "Atish Patra" <atishp@atishpatra.org>, "Björn Töpel" <bjorn@rivosinc.com>, "Suzuki K Poulose" <suzuki.poulose@arm.com>, "Will Deacon" <will@kernel.org>, "Marc Zyngier" <maz@kernel.org>, "Sean Christopherson" <seanjc@google.com>, linux-coco@lists.linux.dev, "Dylan Reid" <dylan@rivosinc.com>, abrestic@rivosinc.com, "Samuel Ortiz" <sameo@rivosinc.com>, "Christoph Hellwig" <hch@infradead.org>, "Conor Dooley" <conor.dooley@microchip.com>, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "Guo Ren" <guoren@kernel.org>, "Heiko Stuebner" <heiko@sntech.de>, "Jiri Slaby" <jirislaby@kernel.org>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, "Mayuresh Chitale" <mchitale@ventanamicro.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Rajnesh Kanwal" <rkanwal@rivosinc.com>, "Uladzislau Rezki" <urezki@gmail.com> Subject: [RFC 23/48] RISC-V: KVM: Wireup TVM world switch Date: Wed, 19 Apr 2023 15:16:51 -0700 [thread overview] Message-ID: <20230419221716.3603068-24-atishp@rivosinc.com> (raw) In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> TVM worlds switch takes a different path from regular VM world switch as it needs to make an ecall to TSM and TSM actually does the world switch. The host doesn't need to save/restore any context as TSM is expected to do that on behalf of the host. The TSM updatess the trap information in the shared memory which host uses to figure out the cause of the guest exit. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/kvm/cove.c | 31 +++++++++++++++++++++++++++++-- arch/riscv/kvm/vcpu.c | 11 +++++++++++ arch/riscv/kvm/vcpu_exit.c | 10 ++++++++++ 3 files changed, 50 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kvm/cove.c b/arch/riscv/kvm/cove.c index c93de9b..c11db7a 100644 --- a/arch/riscv/kvm/cove.c +++ b/arch/riscv/kvm/cove.c @@ -275,9 +275,36 @@ int kvm_riscv_cove_gstage_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hv return rc; } -void kvm_riscv_cove_vcpu_switchto(struct kvm_vcpu *vcpu, struct kvm_cpu_trap *trap) +void noinstr kvm_riscv_cove_vcpu_switchto(struct kvm_vcpu *vcpu, struct kvm_cpu_trap *trap) { - /* TODO */ + int rc; + struct kvm *kvm = vcpu->kvm; + struct kvm_cove_tvm_context *tvmc; + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + void *nshmem; + + if (!kvm->arch.tvmc) + return; + + tvmc = kvm->arch.tvmc; + + nshmem = nacl_shmem(); + /* Invoke finalize to mark TVM is ready run for the first time */ + if (unlikely(!tvmc->finalized_done)) { + + rc = sbi_covh_tsm_finalize_tvm(tvmc->tvm_guest_id, cntx->sepc, cntx->a1); + if (rc) { + kvm_err("TVM Finalized failed with %d\n", rc); + return; + } + tvmc->finalized_done = true; + } + + rc = sbi_covh_run_tvm_vcpu(tvmc->tvm_guest_id, vcpu->vcpu_idx); + if (rc) { + trap->scause = EXC_CUSTOM_KVM_COVE_RUN_FAIL; + return; + } } void kvm_riscv_cove_vcpu_destroy(struct kvm_vcpu *vcpu) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 3e04b78..43a0b8c 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -1042,6 +1042,11 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) kvm_riscv_vcpu_timer_save(vcpu); if (kvm_riscv_nacl_available()) { + /** + * For TVMs, we don't need a separate case as TSM only updates + * the required CSRs during the world switch. All other CSR + * value should be zeroed out by TSM anyways. + */ nshmem = nacl_shmem(); csr->vsstatus = nacl_shmem_csr_read(nshmem, CSR_VSSTATUS); csr->vsie = nacl_shmem_csr_read(nshmem, CSR_VSIE); @@ -1191,6 +1196,12 @@ static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu, gcntx->hstatus = csr_swap(CSR_HSTATUS, hcntx->hstatus); } + trap->htval = nacl_shmem_csr_read(nshmem, CSR_HTVAL); + trap->htinst = nacl_shmem_csr_read(nshmem, CSR_HTINST); + } else if (is_cove_vcpu(vcpu)) { + nshmem = nacl_shmem(); + kvm_riscv_cove_vcpu_switchto(vcpu, trap); + trap->htval = nacl_shmem_csr_read(nshmem, CSR_HTVAL); trap->htinst = nacl_shmem_csr_read(nshmem, CSR_HTINST); } else { diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index 8944e29..c46e7f2 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -218,6 +218,15 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, else if (vcpu->arch.guest_context.hstatus & HSTATUS_SPV) ret = kvm_riscv_vcpu_sbi_ecall(vcpu, run); break; + case EXC_CUSTOM_KVM_COVE_RUN_FAIL: + if (likely(is_cove_vcpu(vcpu))) { + ret = -EACCES; + run->fail_entry.hardware_entry_failure_reason = + KVM_EXIT_FAIL_ENTRY_COVE_RUN_VCPU; + run->fail_entry.cpu = vcpu->cpu; + run->exit_reason = KVM_EXIT_FAIL_ENTRY; + } + break; default: break; } @@ -225,6 +234,7 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, /* Print details in-case of error */ if (ret < 0) { kvm_err("VCPU exit error %d\n", ret); + //TODO: These values are bogus/stale for a TVM. Improve it kvm_err("SEPC=0x%lx SSTATUS=0x%lx HSTATUS=0x%lx\n", vcpu->arch.guest_context.sepc, vcpu->arch.guest_context.sstatus, -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: "Atish Patra" <atishp@rivosinc.com>, "Alexandre Ghiti" <alex@ghiti.fr>, "Andrew Jones" <ajones@ventanamicro.com>, "Andrew Morton" <akpm@linux-foundation.org>, "Anup Patel" <anup@brainfault.org>, "Atish Patra" <atishp@atishpatra.org>, "Björn Töpel" <bjorn@rivosinc.com>, "Suzuki K Poulose" <suzuki.poulose@arm.com>, "Will Deacon" <will@kernel.org>, "Marc Zyngier" <maz@kernel.org>, "Sean Christopherson" <seanjc@google.com>, linux-coco@lists.linux.dev, "Dylan Reid" <dylan@rivosinc.com>, abrestic@rivosinc.com, "Samuel Ortiz" <sameo@rivosinc.com>, "Christoph Hellwig" <hch@infradead.org>, "Conor Dooley" <conor.dooley@microchip.com>, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "Guo Ren" <guoren@kernel.org>, "Heiko Stuebner" <heiko@sntech.de>, "Jiri Slaby" <jirislaby@kernel.org>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, "Mayuresh Chitale" <mchitale@ventanamicro.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "Rajnesh Kanwal" <rkanwal@rivosinc.com>, "Uladzislau Rezki" <urezki@gmail.com> Subject: [RFC 23/48] RISC-V: KVM: Wireup TVM world switch Date: Wed, 19 Apr 2023 15:16:51 -0700 [thread overview] Message-ID: <20230419221716.3603068-24-atishp@rivosinc.com> (raw) In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> TVM worlds switch takes a different path from regular VM world switch as it needs to make an ecall to TSM and TSM actually does the world switch. The host doesn't need to save/restore any context as TSM is expected to do that on behalf of the host. The TSM updatess the trap information in the shared memory which host uses to figure out the cause of the guest exit. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/kvm/cove.c | 31 +++++++++++++++++++++++++++++-- arch/riscv/kvm/vcpu.c | 11 +++++++++++ arch/riscv/kvm/vcpu_exit.c | 10 ++++++++++ 3 files changed, 50 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kvm/cove.c b/arch/riscv/kvm/cove.c index c93de9b..c11db7a 100644 --- a/arch/riscv/kvm/cove.c +++ b/arch/riscv/kvm/cove.c @@ -275,9 +275,36 @@ int kvm_riscv_cove_gstage_map(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned long hv return rc; } -void kvm_riscv_cove_vcpu_switchto(struct kvm_vcpu *vcpu, struct kvm_cpu_trap *trap) +void noinstr kvm_riscv_cove_vcpu_switchto(struct kvm_vcpu *vcpu, struct kvm_cpu_trap *trap) { - /* TODO */ + int rc; + struct kvm *kvm = vcpu->kvm; + struct kvm_cove_tvm_context *tvmc; + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + void *nshmem; + + if (!kvm->arch.tvmc) + return; + + tvmc = kvm->arch.tvmc; + + nshmem = nacl_shmem(); + /* Invoke finalize to mark TVM is ready run for the first time */ + if (unlikely(!tvmc->finalized_done)) { + + rc = sbi_covh_tsm_finalize_tvm(tvmc->tvm_guest_id, cntx->sepc, cntx->a1); + if (rc) { + kvm_err("TVM Finalized failed with %d\n", rc); + return; + } + tvmc->finalized_done = true; + } + + rc = sbi_covh_run_tvm_vcpu(tvmc->tvm_guest_id, vcpu->vcpu_idx); + if (rc) { + trap->scause = EXC_CUSTOM_KVM_COVE_RUN_FAIL; + return; + } } void kvm_riscv_cove_vcpu_destroy(struct kvm_vcpu *vcpu) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 3e04b78..43a0b8c 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -1042,6 +1042,11 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) kvm_riscv_vcpu_timer_save(vcpu); if (kvm_riscv_nacl_available()) { + /** + * For TVMs, we don't need a separate case as TSM only updates + * the required CSRs during the world switch. All other CSR + * value should be zeroed out by TSM anyways. + */ nshmem = nacl_shmem(); csr->vsstatus = nacl_shmem_csr_read(nshmem, CSR_VSSTATUS); csr->vsie = nacl_shmem_csr_read(nshmem, CSR_VSIE); @@ -1191,6 +1196,12 @@ static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu, gcntx->hstatus = csr_swap(CSR_HSTATUS, hcntx->hstatus); } + trap->htval = nacl_shmem_csr_read(nshmem, CSR_HTVAL); + trap->htinst = nacl_shmem_csr_read(nshmem, CSR_HTINST); + } else if (is_cove_vcpu(vcpu)) { + nshmem = nacl_shmem(); + kvm_riscv_cove_vcpu_switchto(vcpu, trap); + trap->htval = nacl_shmem_csr_read(nshmem, CSR_HTVAL); trap->htinst = nacl_shmem_csr_read(nshmem, CSR_HTINST); } else { diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index 8944e29..c46e7f2 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -218,6 +218,15 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, else if (vcpu->arch.guest_context.hstatus & HSTATUS_SPV) ret = kvm_riscv_vcpu_sbi_ecall(vcpu, run); break; + case EXC_CUSTOM_KVM_COVE_RUN_FAIL: + if (likely(is_cove_vcpu(vcpu))) { + ret = -EACCES; + run->fail_entry.hardware_entry_failure_reason = + KVM_EXIT_FAIL_ENTRY_COVE_RUN_VCPU; + run->fail_entry.cpu = vcpu->cpu; + run->exit_reason = KVM_EXIT_FAIL_ENTRY; + } + break; default: break; } @@ -225,6 +234,7 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, /* Print details in-case of error */ if (ret < 0) { kvm_err("VCPU exit error %d\n", ret); + //TODO: These values are bogus/stale for a TVM. Improve it kvm_err("SEPC=0x%lx SSTATUS=0x%lx HSTATUS=0x%lx\n", vcpu->arch.guest_context.sepc, vcpu->arch.guest_context.sstatus, -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-04-19 22:18 UTC|newest] Thread overview: 134+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-19 22:16 [RFC 00/48] RISC-V CoVE support Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 01/48] mm/vmalloc: Introduce arch hooks to notify ioremap/unmap changes Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-20 19:42 ` Lorenzo Stoakes 2023-04-20 19:42 ` Lorenzo Stoakes 2023-04-20 22:01 ` Atish Kumar Patra 2023-04-20 22:01 ` Atish Kumar Patra 2023-04-19 22:16 ` [RFC 02/48] RISC-V: KVM: Improve KVM error reporting to the user space Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 03/48] RISC-V: KVM: Invoke aia_update with preempt disabled/irq enabled Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 04/48] RISC-V: KVM: Add a helper function to get pgd size Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 05/48] RISC-V: Add COVH SBI extensions definitions Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 06/48] RISC-V: KVM: Implement COVH SBI extension Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 07/48] RISC-V: KVM: Add a barebone CoVE implementation Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 08/48] RISC-V: KVM: Add UABI to support static memory region attestation Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 09/48] RISC-V: KVM: Add CoVE related nacl helpers Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 10/48] RISC-V: KVM: Implement static memory region measurement Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-20 15:17 ` Sean Christopherson 2023-04-20 15:17 ` Sean Christopherson 2023-04-21 18:50 ` Atish Kumar Patra 2023-04-21 18:50 ` Atish Kumar Patra 2023-04-19 22:16 ` [RFC 11/48] RISC-V: KVM: Use the new VM IOCTL for measuring pages Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 12/48] RISC-V: KVM: Exit to the user space for trap redirection Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 13/48] RISC-V: KVM: Return early for gstage modifications Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 14/48] RISC-V: KVM: Skip dirty logging updates for TVM Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 15/48] RISC-V: KVM: Add a helper function to trigger fence ops Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 16/48] RISC-V: KVM: Skip most VCPU requests for TVMs Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 17/48] RISC-V : KVM: Skip vmid/hgatp management " Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 18/48] RISC-V: KVM: Skip TLB " Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 19/48] RISC-V: KVM: Register memory regions as confidential " Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 20/48] RISC-V: KVM: Add gstage mapping " Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 21/48] RISC-V: KVM: Handle SBI call forward from the TSM Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 22/48] RISC-V: KVM: Implement vcpu load/put functions for CoVE guests Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` Atish Patra [this message] 2023-04-19 22:16 ` [RFC 23/48] RISC-V: KVM: Wireup TVM world switch Atish Patra 2023-04-19 22:16 ` [RFC 24/48] RISC-V: KVM: Update timer functionality for TVMs Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 25/48] RISC-V: KVM: Skip HVIP update " Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 26/48] RISC-V: Add COVI extension definitions Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 27/48] RISC-V: KVM: Implement COVI SBI extension Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 28/48] RISC-V: KVM: Add interrupt management functions for TVM Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 29/48] RISC-V: KVM: Skip AIA CSR updates for TVMs Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 30/48] RISC-V: KVM: Perform limited operations in hardware enable/disable Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:16 ` [RFC 31/48] RISC-V: KVM: Indicate no support user space emulated IRQCHIP Atish Patra 2023-04-19 22:16 ` Atish Patra 2023-04-19 22:17 ` [RFC 32/48] RISC-V: KVM: Add AIA support for TVMs Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 33/48] RISC-V: KVM: Hookup TVM VCPU init/destroy Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 34/48] RISC-V: KVM: Initialize CoVE Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 35/48] RISC-V: KVM: Add TVM init/destroy calls Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 36/48] RISC-V: KVM: Read/write gprs from/to shmem in case of TVM VCPU Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 37/48] RISC-V: Add COVG SBI extension definitions Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 38/48] RISC-V: Add CoVE guest config and helper functions Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 39/48] RISC-V: Implement COVG SBI extension Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 40/48] RISC-V: COVE: Add COVH invalidate, validate, promote, demote and remove APIs Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 41/48] RISC-V: KVM: Add host side support to handle COVG SBI calls Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 42/48] RISC-V: Allow host to inject any ext interrupt id to a CoVE guest Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 43/48] RISC-V: Add base memory encryption functions Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 44/48] RISC-V: Add cc_platform_has() for RISC-V for CoVE Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 45/48] RISC-V: ioremap: Implement for arch specific ioremap hooks Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-20 22:15 ` Dave Hansen 2023-04-20 22:15 ` Dave Hansen 2023-04-21 19:24 ` Atish Kumar Patra 2023-04-21 19:24 ` Atish Kumar Patra 2023-04-24 13:48 ` Dave Hansen 2023-04-24 13:48 ` Dave Hansen 2023-04-25 8:00 ` Atish Kumar Patra 2023-04-25 8:00 ` Atish Kumar Patra 2023-04-25 13:10 ` Dave Hansen 2023-04-25 13:10 ` Dave Hansen 2023-04-26 8:02 ` Atish Kumar Patra 2023-04-26 8:02 ` Atish Kumar Patra 2023-04-26 10:30 ` Anup Patel 2023-04-26 10:30 ` Anup Patel 2023-04-26 13:55 ` Andrew Bresticker 2023-04-26 13:55 ` Andrew Bresticker 2023-04-19 22:17 ` [RFC 46/48] riscv/virtio: Have CoVE guests enforce restricted virtio memory access Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 47/48] RISC-V: Add shared bounce buffer to support DBCN for CoVE Guest Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:17 ` [RFC 48/48] drivers/hvc: sbi: Disable HVC console for TVMs Atish Patra 2023-04-19 22:17 ` Atish Patra 2023-04-19 22:58 ` [RFC 00/48] RISC-V CoVE support Atish Patra 2023-04-19 22:58 ` Atish Patra 2023-04-20 16:30 ` Sean Christopherson 2023-04-20 16:30 ` Sean Christopherson 2023-04-20 19:13 ` Atish Kumar Patra 2023-04-20 19:13 ` Atish Kumar Patra 2023-04-20 20:21 ` Sean Christopherson 2023-04-20 20:21 ` Sean Christopherson 2023-04-21 15:35 ` Michael Roth 2023-04-21 15:35 ` Michael Roth 2023-04-24 12:23 ` Christophe de Dinechin 2023-04-24 12:23 ` Christophe de Dinechin
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