From: Mason Huo <mason.huo@starfivetech.com> To: "Rafael J. Wysocki" <rafael@kernel.org>, Viresh Kumar <viresh.kumar@linaro.org>, Emil Renner Berthing <kernel@esmil.dk>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor@kernel.org>, "Paul Walmsley" <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: Shengyu Qu <wiagn233@outlook.com>, <linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>, Mason Huo <mason.huo@starfivetech.com> Subject: [PATCH v3 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Date: Fri, 21 Apr 2023 11:14:31 +0800 [thread overview] Message-ID: <20230421031431.23010-4-mason.huo@starfivetech.com> (raw) In-Reply-To: <20230421031431.23010-1-mason.huo@starfivetech.com> Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC. It supports up to 4 cpu frequency loads. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> --- .../jh7110-starfive-visionfive-2.dtsi | 16 +++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index cca1c8040801..43a9dbb839d2 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -227,3 +227,19 @@ &uart0 { pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&U74_1 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_2 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_3 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_4 { + cpu-supply = <&vdd_cpu>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..7eef88d2cedb 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -53,6 +53,9 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -79,6 +82,9 @@ U74_2: cpu@2 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -105,6 +111,9 @@ U74_3: cpu@3 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -131,6 +140,9 @@ U74_4: cpu@4 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -164,6 +176,27 @@ core4 { }; }; + cpu_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <800000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <800000>; + }; + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-microvolt = <800000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1040000>; + }; + }; + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { compatible = "fixed-clock"; clock-output-names = "gmac0_rgmii_rxin"; -- 2.39.2
WARNING: multiple messages have this Message-ID (diff)
From: Mason Huo <mason.huo@starfivetech.com> To: "Rafael J. Wysocki" <rafael@kernel.org>, Viresh Kumar <viresh.kumar@linaro.org>, Emil Renner Berthing <kernel@esmil.dk>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor@kernel.org>, "Paul Walmsley" <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: Shengyu Qu <wiagn233@outlook.com>, <linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>, Mason Huo <mason.huo@starfivetech.com> Subject: [PATCH v3 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Date: Fri, 21 Apr 2023 11:14:31 +0800 [thread overview] Message-ID: <20230421031431.23010-4-mason.huo@starfivetech.com> (raw) In-Reply-To: <20230421031431.23010-1-mason.huo@starfivetech.com> Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC. It supports up to 4 cpu frequency loads. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> --- .../jh7110-starfive-visionfive-2.dtsi | 16 +++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index cca1c8040801..43a9dbb839d2 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -227,3 +227,19 @@ &uart0 { pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&U74_1 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_2 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_3 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_4 { + cpu-supply = <&vdd_cpu>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..7eef88d2cedb 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -53,6 +53,9 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -79,6 +82,9 @@ U74_2: cpu@2 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -105,6 +111,9 @@ U74_3: cpu@3 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -131,6 +140,9 @@ U74_4: cpu@4 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -164,6 +176,27 @@ core4 { }; }; + cpu_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <800000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <800000>; + }; + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-microvolt = <800000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1040000>; + }; + }; + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { compatible = "fixed-clock"; clock-output-names = "gmac0_rgmii_rxin"; -- 2.39.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-04-21 3:15 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-21 3:14 [PATCH v3 0/3] Add JH7110 cpufreq support Mason Huo 2023-04-21 3:14 ` Mason Huo 2023-04-21 3:14 ` [PATCH v3 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo 2023-04-21 3:14 ` Mason Huo 2023-04-21 3:14 ` [PATCH v3 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo 2023-04-21 3:14 ` Mason Huo 2023-04-21 7:37 ` Viresh Kumar 2023-04-21 7:37 ` Viresh Kumar 2023-04-21 3:14 ` Mason Huo [this message] 2023-04-21 3:14 ` [PATCH v3 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo 2023-05-05 1:38 ` [PATCH v3 0/3] Add JH7110 cpufreq support Mason Huo 2023-05-05 1:38 ` Mason Huo 2023-05-05 6:29 ` Conor Dooley 2023-05-05 6:29 ` Conor Dooley 2023-06-05 9:36 ` Mason Huo 2023-06-05 9:36 ` Mason Huo 2023-06-05 9:54 ` Conor Dooley 2023-06-05 9:54 ` Conor Dooley
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