From: fei.yang@intel.com To: intel-gfx@lists.freedesktop.org Cc: Fei Yang <fei.yang@intel.com>, jordan.l.justen@intel.com, lionel.g.landwerlin@intel.com, dri-devel@lists.freedesktop.org, Andrzej Hajda <andrzej.hajda@intel.com>, Andi Shyti <andi.shyti@linux.intel.com> Subject: [PATCH v1 5/6] drm/i915/mtl: end support for set caching ioctl Date: Sun, 23 Apr 2023 21:42:50 -0700 [thread overview] Message-ID: <20230424044251.3390364-6-fei.yang@intel.com> (raw) In-Reply-To: <20230424044251.3390364-1-fei.yang@intel.com> From: Fei Yang <fei.yang@intel.com> The design is to keep Buffer Object's caching policy immutable through out its life cycle. This patch ends the support for set caching ioctl from MTL onward. While doing that we also set BO's to be 1-way coherent at creation time because GPU is no longer automatically snooping CPU cache. For userspace components needing to fine tune the caching policy for BO's, a follow up patch will extend the GEM_CREATE uAPI to allow them specify caching mode at BO creation time. Signed-off-by: Fei Yang <fei.yang@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++ drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 89938084af97..d5fd4c9cd9f8 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -328,6 +328,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, if (IS_DGFX(i915)) return -ENODEV; + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + return -EOPNOTSUPP; + switch (args->caching) { case I915_CACHING_NONE: level = I915_CACHE_NONE; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index 37d1efcd3ca6..cad4a6017f4b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem, obj->write_domain = I915_GEM_DOMAIN_CPU; obj->read_domains = I915_GEM_DOMAIN_CPU; - if (HAS_LLC(i915)) + /* + * MTL doesn't snoop CPU cache by default for GPU access (namely + * 1-way coherency). However some UMD's are currently depending on + * that. Make 1-way coherent the default setting for MTL. A follow + * up patch will extend the GEM_CREATE uAPI to allow UMD's specify + * caching mode at BO creation time + */ + if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))) /* On some devices, we can have the GPU use the LLC (the CPU * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: fei.yang@intel.com To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Andrzej Hajda <andrzej.hajda@intel.com> Subject: [Intel-gfx] [PATCH v1 5/6] drm/i915/mtl: end support for set caching ioctl Date: Sun, 23 Apr 2023 21:42:50 -0700 [thread overview] Message-ID: <20230424044251.3390364-6-fei.yang@intel.com> (raw) In-Reply-To: <20230424044251.3390364-1-fei.yang@intel.com> From: Fei Yang <fei.yang@intel.com> The design is to keep Buffer Object's caching policy immutable through out its life cycle. This patch ends the support for set caching ioctl from MTL onward. While doing that we also set BO's to be 1-way coherent at creation time because GPU is no longer automatically snooping CPU cache. For userspace components needing to fine tune the caching policy for BO's, a follow up patch will extend the GEM_CREATE uAPI to allow them specify caching mode at BO creation time. Signed-off-by: Fei Yang <fei.yang@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++ drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 89938084af97..d5fd4c9cd9f8 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -328,6 +328,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, if (IS_DGFX(i915)) return -ENODEV; + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + return -EOPNOTSUPP; + switch (args->caching) { case I915_CACHING_NONE: level = I915_CACHE_NONE; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index 37d1efcd3ca6..cad4a6017f4b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem, obj->write_domain = I915_GEM_DOMAIN_CPU; obj->read_domains = I915_GEM_DOMAIN_CPU; - if (HAS_LLC(i915)) + /* + * MTL doesn't snoop CPU cache by default for GPU access (namely + * 1-way coherency). However some UMD's are currently depending on + * that. Make 1-way coherent the default setting for MTL. A follow + * up patch will extend the GEM_CREATE uAPI to allow UMD's specify + * caching mode at BO creation time + */ + if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))) /* On some devices, we can have the GPU use the LLC (the CPU * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than -- 2.25.1
next prev parent reply other threads:[~2023-04-24 4:42 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-24 4:42 [PATCH v1 0/6] drm/i915: Allow user to set cache at BO creation fei.yang 2023-04-24 4:42 ` [Intel-gfx] " fei.yang 2023-04-24 4:42 ` [PATCH v1 1/6] drm/i915/mtl: Add PTE encode function fei.yang 2023-04-24 4:42 ` [Intel-gfx] " fei.yang 2023-04-24 4:42 ` [PATCH v1 2/6] drm/i915: preparation for using PAT index fei.yang 2023-04-24 4:42 ` [Intel-gfx] " fei.yang 2023-04-24 4:42 ` [PATCH v1 3/6] drm/i915: use pat_index instead of cache_level fei.yang 2023-04-24 4:42 ` [Intel-gfx] " fei.yang 2023-04-24 4:42 ` [PATCH v1 4/6] drm/i915: make sure correct pte encode is used fei.yang 2023-04-24 4:42 ` [Intel-gfx] " fei.yang 2023-04-24 4:42 ` fei.yang [this message] 2023-04-24 4:42 ` [Intel-gfx] [PATCH v1 5/6] drm/i915/mtl: end support for set caching ioctl fei.yang 2023-04-24 4:42 ` [PATCH v1 6/6] drm/i915: Allow user to set cache at BO creation fei.yang 2023-04-24 4:42 ` [Intel-gfx] " fei.yang 2023-04-24 5:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork 2023-04-24 5:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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