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From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Manivannan Sadhasivam <mani@kernel.org>,
	"Borislav Petkov (AMD)" <bp@alien8.de>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Konrad Dybcio <konrad.dybcio@linaro.org>
Subject: [PATCH 2/2] arm64: dts: qcom: sm8550: Use the correct LLCC register scheme
Date: Wed, 17 May 2023 04:18:50 +0200	[thread overview]
Message-ID: <20230517-topic-kailua-llcc-v1-2-d57bd860c43e@linaro.org> (raw)
In-Reply-To: <20230517-topic-kailua-llcc-v1-0-d57bd860c43e@linaro.org>

During the ABI-breaking (for good reasons) conversion of the LLCC
register description, SM8550 was not taken into account, resulting
in LLCC being broken on any kernel containing the patch referenced
in the fixes tag.

Fix it by describing the regions properly.

Fixes: ee13b5008707 ("qcom: llcc/edac: Fix the base address used for accessing LLCC banks")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 6e9bad8f6f33..70ae7e2e900a 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3762,9 +3762,16 @@ gem_noc: interconnect@24100000 {
 
 		system-cache-controller@25000000 {
 			compatible = "qcom,sm8550-llcc";
-			reg = <0 0x25000000 0 0x800000>,
+			reg = <0 0x25000000 0 0x200000>,
+			      <0 0x25200000 0 0x200000>,
+			      <0 0x25400000 0 0x200000>,
+			      <0 0x25600000 0 0x200000>,
 			      <0 0x25800000 0 0x200000>;
-			reg-names = "llcc_base", "llcc_broadcast_base";
+			reg-names = "llcc0_base",
+				    "llcc1_base",
+				    "llcc2_base",
+				    "llcc3_base",
+				    "llcc_broadcast_base";
 			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		};
 

-- 
2.40.1


  parent reply	other threads:[~2023-05-17  2:19 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-17  2:18 [PATCH 0/2] Fix SM8550 LLCC Konrad Dybcio
2023-05-17  2:18 ` [PATCH 1/2] dt-bindings: cache: qcom,llcc: Fix SM8550 description Konrad Dybcio
2023-05-17  5:44   ` Manivannan Sadhasivam
2023-05-17 13:20     ` Konrad Dybcio
2023-05-17  7:52   ` Krzysztof Kozlowski
2023-05-17  8:46   ` Krzysztof Kozlowski
2023-05-17  2:18 ` Konrad Dybcio [this message]
2023-05-17  5:47   ` [PATCH 2/2] arm64: dts: qcom: sm8550: Use the correct LLCC register scheme Manivannan Sadhasivam
2023-05-25  4:53 ` (subset) [PATCH 0/2] Fix SM8550 LLCC Bjorn Andersson

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