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From: fei.yang@intel.com
To: intel-gfx@lists.freedesktop.org
Cc: Andrzej Hajda <andrzej.hajda@intel.com>,
	Fei Yang <fei.yang@intel.com>,
	dri-devel@lists.freedesktop.org,
	Andi Shyti <andi.shyti@linux.intel.com>
Subject: [PATCH v10 1/2] drm/i915/mtl: end support for set caching ioctl
Date: Thu, 18 May 2023 22:11:02 -0700	[thread overview]
Message-ID: <20230519051103.3404990-2-fei.yang@intel.com> (raw)
In-Reply-To: <20230519051103.3404990-1-fei.yang@intel.com>

From: Fei Yang <fei.yang@intel.com>

The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
cache. For userspace components needing to fine tune the caching policy
for BO's, a follow up patch will extend the GEM_CREATE uAPI to allow
them specify caching mode at BO creation time.

Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c  | 9 ++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 05107a6efe45..dfaaa8b66ac3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -350,6 +350,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
 	if (IS_DGFX(i915))
 		return -ENODEV;
 
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+		return -EOPNOTSUPP;
+
 	switch (args->caching) {
 	case I915_CACHING_NONE:
 		level = I915_CACHE_NONE;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 37d1efcd3ca6..cad4a6017f4b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem,
 	obj->write_domain = I915_GEM_DOMAIN_CPU;
 	obj->read_domains = I915_GEM_DOMAIN_CPU;
 
-	if (HAS_LLC(i915))
+	/*
+	 * MTL doesn't snoop CPU cache by default for GPU access (namely
+	 * 1-way coherency). However some UMD's are currently depending on
+	 * that. Make 1-way coherent the default setting for MTL. A follow
+	 * up patch will extend the GEM_CREATE uAPI to allow UMD's specify
+	 * caching mode at BO creation time
+	 */
+	if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)))
 		/* On some devices, we can have the GPU use the LLC (the CPU
 		 * cache) for about a 10% performance improvement
 		 * compared to uncached.  Graphics requests other than
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: fei.yang@intel.com
To: intel-gfx@lists.freedesktop.org
Cc: Andrzej Hajda <andrzej.hajda@intel.com>, dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v10 1/2] drm/i915/mtl: end support for set caching ioctl
Date: Thu, 18 May 2023 22:11:02 -0700	[thread overview]
Message-ID: <20230519051103.3404990-2-fei.yang@intel.com> (raw)
In-Reply-To: <20230519051103.3404990-1-fei.yang@intel.com>

From: Fei Yang <fei.yang@intel.com>

The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
cache. For userspace components needing to fine tune the caching policy
for BO's, a follow up patch will extend the GEM_CREATE uAPI to allow
them specify caching mode at BO creation time.

Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c  | 9 ++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 05107a6efe45..dfaaa8b66ac3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -350,6 +350,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
 	if (IS_DGFX(i915))
 		return -ENODEV;
 
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+		return -EOPNOTSUPP;
+
 	switch (args->caching) {
 	case I915_CACHING_NONE:
 		level = I915_CACHE_NONE;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 37d1efcd3ca6..cad4a6017f4b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem,
 	obj->write_domain = I915_GEM_DOMAIN_CPU;
 	obj->read_domains = I915_GEM_DOMAIN_CPU;
 
-	if (HAS_LLC(i915))
+	/*
+	 * MTL doesn't snoop CPU cache by default for GPU access (namely
+	 * 1-way coherency). However some UMD's are currently depending on
+	 * that. Make 1-way coherent the default setting for MTL. A follow
+	 * up patch will extend the GEM_CREATE uAPI to allow UMD's specify
+	 * caching mode at BO creation time
+	 */
+	if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)))
 		/* On some devices, we can have the GPU use the LLC (the CPU
 		 * cache) for about a 10% performance improvement
 		 * compared to uncached.  Graphics requests other than
-- 
2.25.1


  reply	other threads:[~2023-05-19  5:10 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-19  5:11 [PATCH v10 0/2] drm/i915: Allow user to set cache at BO creation fei.yang
2023-05-19  5:11 ` [Intel-gfx] " fei.yang
2023-05-19  5:11 ` fei.yang [this message]
2023-05-19  5:11   ` [Intel-gfx] [PATCH v10 1/2] drm/i915/mtl: end support for set caching ioctl fei.yang
2023-05-19  5:11 ` [PATCH v10 2/2] drm/i915: Allow user to set cache at BO creation fei.yang
2023-05-19  5:11   ` [Intel-gfx] " fei.yang
2023-05-21  4:30   ` Jordan Justen
2023-05-21  4:30     ` [Intel-gfx] " Jordan Justen
2023-05-25 11:42     ` Extension detection by enumeration vs attempt to use extension (Was: Re: [Intel-gfx] [PATCH v10 2/2] drm/i915: Allow user to set cache at BO creation) Joonas Lahtinen
2023-05-25 11:42       ` [Intel-gfx] Extension detection by enumeration vs attempt to use extension (Was: " Joonas Lahtinen
2023-05-22 11:52   ` [PATCH v10 2/2] drm/i915: Allow user to set cache at BO creation Andi Shyti
2023-05-22 11:52     ` [Intel-gfx] " Andi Shyti
2023-05-22 15:25     ` Jordan Justen
2023-05-22 15:25       ` [Intel-gfx] " Jordan Justen
2023-05-22 15:30       ` Andi Shyti
2023-05-22 15:30         ` [Intel-gfx] " Andi Shyti
2023-05-19  5:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Allow user to set cache at BO creation (rev10) Patchwork
2023-05-19  6:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-05-19 10:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-05-23  8:37 ` [Intel-gfx] [PATCH v10 0/2] drm/i915: Allow user to set cache at BO creation Andi Shyti
2023-05-23  8:37   ` Andi Shyti
2023-05-24 11:56   ` Tvrtko Ursulin
2023-05-24 11:56     ` Tvrtko Ursulin
2023-05-24 12:05     ` Tvrtko Ursulin
2023-05-24 12:05       ` Tvrtko Ursulin
2023-05-24 12:19     ` Andi Shyti
2023-05-24 12:19       ` Andi Shyti
2023-05-24 12:30       ` Andi Shyti
2023-05-24 12:30         ` Andi Shyti
2023-05-24 12:52         ` Tvrtko Ursulin
2023-05-24 12:52           ` Tvrtko Ursulin
2023-05-24 12:34       ` Tvrtko Ursulin
2023-05-24 12:34         ` Tvrtko Ursulin

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