From: Adam Ford <aford173@gmail.com> To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford <aford173@gmail.com>, Chen-Yu Tsai <wenst@chromium.org>, Frieder Schrempf <frieder.schrempf@kontron.de>, Marek Szyprowski <m.szyprowski@samsung.com>, Jagan Teki <jagan@amarulasolutions.com>, Inki Dae <inki.dae@samsung.com>, Andrzej Hajda <andrzej.hajda@intel.com>, Neil Armstrong <neil.armstrong@linaro.org>, Robert Foss <rfoss@kernel.org>, Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, Jonas Karlman <jonas@kwiboo.se>, Jernej Skrabec <jernej.skrabec@gmail.com>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Marek Vasut <marex@denx.de>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V8 6/7] drm: bridge: samsung-dsim: Support non-burst mode Date: Thu, 25 May 2023 22:05:58 -0500 [thread overview] Message-ID: <20230526030559.326566-7-aford173@gmail.com> (raw) In-Reply-To: <20230526030559.326566-1-aford173@gmail.com> The high-speed clock is hard-coded to the burst-clock frequency specified in the device tree. However, when using devices like certain bridge chips without burst mode and varying resolutions and refresh rates, it may be necessary to set the high-speed clock dynamically based on the desired pixel clock for the connected device. This also removes the need to set a clock speed from the device tree for non-burst mode operation, since the pixel clock rate is the rate requested from the attached device like a bridge chip. This should have no impact for people using burst-mode and setting the burst clock rate is still required for those users. If the burst clock is not present, change the error message to dev_info indicating the clock use the pixel clock. Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 41f557fee29a..99ce2690582b 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -667,11 +667,21 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) { - unsigned long hs_clk, byte_clk, esc_clk; + unsigned long hs_clk, byte_clk, esc_clk, pix_clk; unsigned long esc_div; u32 reg; + struct drm_display_mode *m = &dsi->mode; + int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + + /* m->clock is in KHz */ + pix_clk = m->clock * 1000; + + /* Use burst_clk_rate if available, otherwise use the pix_clk */ + if (dsi->burst_clk_rate) + hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); + else + hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes)); - hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); if (!hs_clk) { dev_err(dsi->dev, "failed to configure DSI PLL\n"); return -EFAULT; @@ -943,7 +953,7 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) u32 reg; if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { - int byte_clk_khz = dsi->burst_clk_rate / 1000 / 8; + int byte_clk_khz = dsi->hs_clock / 1000 / 8; int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; @@ -1794,10 +1804,13 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) return PTR_ERR(pll_clk); } + /* If it doesn't exist, use pixel clock instead of failing */ ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", - &dsi->burst_clk_rate, 0); - if (ret < 0) - return ret; + &dsi->burst_clk_rate, 1); + if (ret < 0) { + dev_dbg(dev, "Using pixel clock for HS clock frequency\n"); + dsi->burst_clk_rate = 0; + } ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", &dsi->esc_clk_rate, 0); -- 2.39.2
WARNING: multiple messages have this Message-ID (diff)
From: Adam Ford <aford173@gmail.com> To: dri-devel@lists.freedesktop.org Cc: Marek Vasut <marex@denx.de>, Neil Armstrong <neil.armstrong@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, Robert Foss <rfoss@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Jonas Karlman <jonas@kwiboo.se>, Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, aford@beaconembedded.com, Frieder Schrempf <frieder.schrempf@kontron.de>, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, Jagan Teki <jagan@amarulasolutions.com>, Andrzej Hajda <andrzej.hajda@intel.com>, Chen-Yu Tsai <wenst@chromium.org>, Adam Ford <aford173@gmail.com>, Marek Szyprowski <m.szyprowski@samsung.com> Subject: [PATCH V8 6/7] drm: bridge: samsung-dsim: Support non-burst mode Date: Thu, 25 May 2023 22:05:58 -0500 [thread overview] Message-ID: <20230526030559.326566-7-aford173@gmail.com> (raw) In-Reply-To: <20230526030559.326566-1-aford173@gmail.com> The high-speed clock is hard-coded to the burst-clock frequency specified in the device tree. However, when using devices like certain bridge chips without burst mode and varying resolutions and refresh rates, it may be necessary to set the high-speed clock dynamically based on the desired pixel clock for the connected device. This also removes the need to set a clock speed from the device tree for non-burst mode operation, since the pixel clock rate is the rate requested from the attached device like a bridge chip. This should have no impact for people using burst-mode and setting the burst clock rate is still required for those users. If the burst clock is not present, change the error message to dev_info indicating the clock use the pixel clock. Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 41f557fee29a..99ce2690582b 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -667,11 +667,21 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) { - unsigned long hs_clk, byte_clk, esc_clk; + unsigned long hs_clk, byte_clk, esc_clk, pix_clk; unsigned long esc_div; u32 reg; + struct drm_display_mode *m = &dsi->mode; + int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + + /* m->clock is in KHz */ + pix_clk = m->clock * 1000; + + /* Use burst_clk_rate if available, otherwise use the pix_clk */ + if (dsi->burst_clk_rate) + hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); + else + hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes)); - hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); if (!hs_clk) { dev_err(dsi->dev, "failed to configure DSI PLL\n"); return -EFAULT; @@ -943,7 +953,7 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) u32 reg; if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { - int byte_clk_khz = dsi->burst_clk_rate / 1000 / 8; + int byte_clk_khz = dsi->hs_clock / 1000 / 8; int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; @@ -1794,10 +1804,13 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) return PTR_ERR(pll_clk); } + /* If it doesn't exist, use pixel clock instead of failing */ ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", - &dsi->burst_clk_rate, 0); - if (ret < 0) - return ret; + &dsi->burst_clk_rate, 1); + if (ret < 0) { + dev_dbg(dev, "Using pixel clock for HS clock frequency\n"); + dsi->burst_clk_rate = 0; + } ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", &dsi->esc_clk_rate, 0); -- 2.39.2
next prev parent reply other threads:[~2023-05-26 3:07 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-26 3:05 [PATCH V8 0/7] drm: bridge: samsung-dsim: Support variable clocking Adam Ford 2023-05-26 3:05 ` Adam Ford 2023-05-26 3:05 ` [PATCH V8 1/7] drm: bridge: samsung-dsim: fix blanking packet size calculation Adam Ford 2023-05-26 3:05 ` Adam Ford 2023-05-26 3:05 ` [PATCH V8 2/7] drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp] Adam Ford 2023-05-26 3:05 ` Adam Ford 2023-05-26 3:05 ` [PATCH V8 3/7] drm: bridge: samsung-dsim: Fetch pll-clock-frequency automatically Adam Ford 2023-05-26 3:05 ` Adam Ford 2023-05-26 3:05 ` [PATCH V8 4/7] drm: bridge: samsung-dsim: Select GENERIC_PHY_MIPI_DPHY Adam Ford 2023-05-26 3:05 ` Adam Ford 2023-05-26 3:05 ` [PATCH V8 5/7] drm: bridge: samsung-dsim: Dynamically configure DPHY timing Adam Ford 2023-05-26 3:05 ` Adam Ford 2023-05-26 3:05 ` Adam Ford [this message] 2023-05-26 3:05 ` [PATCH V8 6/7] drm: bridge: samsung-dsim: Support non-burst mode Adam Ford 2023-05-26 3:05 ` [PATCH V8 7/7] dt-bindings: bridge: samsung-dsim: Make some flags optional Adam Ford 2023-05-26 3:05 ` Adam Ford 2023-05-26 18:19 ` Conor Dooley 2023-05-26 18:19 ` Conor Dooley 2023-05-26 19:24 ` Adam Ford 2023-05-26 19:24 ` Adam Ford 2023-05-26 19:30 ` Conor Dooley 2023-05-26 19:30 ` Conor Dooley 2023-05-30 7:48 ` Krzysztof Kozlowski 2023-05-30 7:48 ` Krzysztof Kozlowski 2023-05-26 7:22 ` [PATCH V8 0/7] drm: bridge: samsung-dsim: Support variable clocking Neil Armstrong 2023-05-26 7:22 ` Neil Armstrong 2023-05-26 7:24 ` Neil Armstrong 2023-05-26 7:24 ` Neil Armstrong 2023-05-26 14:04 ` Adam Ford 2023-05-26 14:04 ` Adam Ford 2023-05-30 8:01 ` Neil Armstrong 2023-05-30 8:01 ` Neil Armstrong 2023-06-07 13:15 ` Rasmus Villemoes 2023-06-07 13:15 ` Rasmus Villemoes 2023-06-07 13:27 ` Adam Ford 2023-06-07 13:27 ` Adam Ford 2023-06-07 14:23 ` Adam Ford 2023-06-07 14:23 ` Adam Ford 2023-06-08 11:40 ` Rasmus Villemoes 2023-06-08 11:40 ` Rasmus Villemoes 2023-06-08 12:30 ` Adam Ford 2023-06-08 12:30 ` Adam Ford 2023-06-08 12:52 ` Lucas Stach 2023-06-08 12:52 ` Lucas Stach
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