From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Tony Ye <tony.ye@intel.com>, John Harrison <John.C.Harrison@Intel.com>, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>, Alan Previn <alan.previn.teres.alexis@intel.com>, dri-devel@lists.freedesktop.org Subject: [PATCH v3 0/7] drm/i915: HuC loading and authentication for MTL Date: Fri, 26 May 2023 17:52:35 -0700 [thread overview] Message-ID: <20230527005242.1346093-1-daniele.ceraolospurio@intel.com> (raw) The HuC loading and authentication flow is once again changing and a new "clear-media only" authentication step is introduced. The flow is as follows: 1) The HuC is loaded via DMA - same as all non-GSC HuC binaries. 2) The HuC is authenticated by the GuC - this is the same step as performed for all non-GSC HuC binaries and re-uses the same code, but it is now resulting in a partial authentication that only allows clear-media workloads. 3) The HuC is fully authenticated for all workloads by the GSC - this is done via a new PXP command, submitted via the GSCCS. The advantage of this new flow is that we can start processing clear-media workloads without having to wait for the GSC to be ready, which can take several seconds. As part of this change, the HuC status getparam has been updated with a new value to indicate a partial authentication. Note tha the media driver is checking for value > 0 for clear media workloads, so no changes are required in userspace for that to work. v2: fix HuC auth status check for DG2. v3: addrss review feedback, stop using the "meu" tag for the naming of the headers, better comments Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Acked-by: Tony Ye <tony.ye@intel.com> Daniele Ceraolo Spurio (7): drm/i915/uc: perma-pin firmwares drm/i915/huc: Parse the GSC-enabled HuC binary drm/i915/huc: Load GSC-enabled HuC via DMA xfer if the fuse says so drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flow drm/i915/mtl/huc: auth HuC via GSC drm/i915/mtl/huc: Use the media gt for the HuC getparam drm/i915/huc: define HuC FW version for MTL drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 + .../drm/i915/gt/uc/intel_gsc_binary_headers.h | 74 ++++++ drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 34 ++- .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_huc.c | 201 ++++++++++----- drivers/gpu/drm/i915/gt/uc/intel_huc.h | 26 +- drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 233 +++++++++++++++++- drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 6 +- drivers/gpu/drm/i915/gt/uc/intel_huc_print.h | 21 ++ drivers/gpu/drm/i915/gt/uc/intel_uc.c | 10 +- drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 132 +++++----- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 26 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 6 - drivers/gpu/drm/i915/i915_getparam.c | 6 +- drivers/gpu/drm/i915/i915_reg.h | 3 + .../drm/i915/pxp/intel_pxp_cmd_interface_43.h | 14 +- drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 2 +- include/uapi/drm/i915_drm.h | 3 +- 20 files changed, 654 insertions(+), 152 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_print.h -- 2.40.0
WARNING: multiple messages have this Message-ID (diff)
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Alan Previn <alan.previn.teres.alexis@intel.com>, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v3 0/7] drm/i915: HuC loading and authentication for MTL Date: Fri, 26 May 2023 17:52:35 -0700 [thread overview] Message-ID: <20230527005242.1346093-1-daniele.ceraolospurio@intel.com> (raw) The HuC loading and authentication flow is once again changing and a new "clear-media only" authentication step is introduced. The flow is as follows: 1) The HuC is loaded via DMA - same as all non-GSC HuC binaries. 2) The HuC is authenticated by the GuC - this is the same step as performed for all non-GSC HuC binaries and re-uses the same code, but it is now resulting in a partial authentication that only allows clear-media workloads. 3) The HuC is fully authenticated for all workloads by the GSC - this is done via a new PXP command, submitted via the GSCCS. The advantage of this new flow is that we can start processing clear-media workloads without having to wait for the GSC to be ready, which can take several seconds. As part of this change, the HuC status getparam has been updated with a new value to indicate a partial authentication. Note tha the media driver is checking for value > 0 for clear media workloads, so no changes are required in userspace for that to work. v2: fix HuC auth status check for DG2. v3: addrss review feedback, stop using the "meu" tag for the naming of the headers, better comments Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Acked-by: Tony Ye <tony.ye@intel.com> Daniele Ceraolo Spurio (7): drm/i915/uc: perma-pin firmwares drm/i915/huc: Parse the GSC-enabled HuC binary drm/i915/huc: Load GSC-enabled HuC via DMA xfer if the fuse says so drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flow drm/i915/mtl/huc: auth HuC via GSC drm/i915/mtl/huc: Use the media gt for the HuC getparam drm/i915/huc: define HuC FW version for MTL drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 + .../drm/i915/gt/uc/intel_gsc_binary_headers.h | 74 ++++++ drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 34 ++- .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_huc.c | 201 ++++++++++----- drivers/gpu/drm/i915/gt/uc/intel_huc.h | 26 +- drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 233 +++++++++++++++++- drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 6 +- drivers/gpu/drm/i915/gt/uc/intel_huc_print.h | 21 ++ drivers/gpu/drm/i915/gt/uc/intel_uc.c | 10 +- drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 132 +++++----- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 26 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 6 - drivers/gpu/drm/i915/i915_getparam.c | 6 +- drivers/gpu/drm/i915/i915_reg.h | 3 + .../drm/i915/pxp/intel_pxp_cmd_interface_43.h | 14 +- drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 2 +- include/uapi/drm/i915_drm.h | 3 +- 20 files changed, 654 insertions(+), 152 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_print.h -- 2.40.0
next reply other threads:[~2023-05-27 0:53 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-27 0:52 Daniele Ceraolo Spurio [this message] 2023-05-27 0:52 ` [Intel-gfx] [PATCH v3 0/7] drm/i915: HuC loading and authentication for MTL Daniele Ceraolo Spurio 2023-05-27 0:52 ` [PATCH v3 1/7] drm/i915/uc: perma-pin firmwares Daniele Ceraolo Spurio 2023-05-27 0:52 ` [Intel-gfx] " Daniele Ceraolo Spurio 2023-05-30 22:52 ` John Harrison 2023-05-30 22:52 ` [Intel-gfx] " John Harrison 2023-05-27 0:52 ` [PATCH v3 2/7] drm/i915/huc: Parse the GSC-enabled HuC binary Daniele Ceraolo Spurio 2023-05-27 0:52 ` [Intel-gfx] " Daniele Ceraolo Spurio 2023-05-30 23:30 ` John Harrison 2023-05-30 23:30 ` [Intel-gfx] " John Harrison 2023-05-31 0:06 ` Ceraolo Spurio, Daniele 2023-05-31 0:06 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2023-05-31 0:11 ` John Harrison 2023-05-31 0:11 ` [Intel-gfx] " John Harrison 2023-05-27 0:52 ` [PATCH v3 3/7] drm/i915/huc: Load GSC-enabled HuC via DMA xfer if the fuse says so Daniele Ceraolo Spurio 2023-05-27 0:52 ` [Intel-gfx] " Daniele Ceraolo Spurio 2023-05-30 23:51 ` John Harrison 2023-05-30 23:51 ` [Intel-gfx] " John Harrison 2023-05-31 0:11 ` Ceraolo Spurio, Daniele 2023-05-31 0:11 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2023-05-31 0:20 ` John Harrison 2023-05-31 0:20 ` [Intel-gfx] " John Harrison 2023-05-31 0:26 ` Ceraolo Spurio, Daniele 2023-05-31 0:26 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2023-05-27 0:52 ` [PATCH v3 4/7] drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flow Daniele Ceraolo Spurio 2023-05-27 0:52 ` [Intel-gfx] " Daniele Ceraolo Spurio 2023-05-27 5:07 ` kernel test robot 2023-05-27 8:59 ` kernel test robot 2023-05-30 15:29 ` [PATCH v4] " Daniele Ceraolo Spurio 2023-05-30 15:29 ` [Intel-gfx] " Daniele Ceraolo Spurio 2023-05-31 0:01 ` John Harrison 2023-05-31 0:01 ` [Intel-gfx] " John Harrison 2023-05-31 0:14 ` Ceraolo Spurio, Daniele 2023-05-31 0:14 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2023-05-31 0:24 ` John Harrison 2023-05-31 0:24 ` [Intel-gfx] " John Harrison 2023-05-31 0:53 ` [PATCH v3 4/7] " kernel test robot 2023-05-27 0:52 ` [PATCH v3 5/7] drm/i915/mtl/huc: auth HuC via GSC Daniele Ceraolo Spurio 2023-05-27 0:52 ` [Intel-gfx] " Daniele Ceraolo Spurio 2023-05-31 0:33 ` Teres Alexis, Alan Previn 2023-05-31 0:33 ` [Intel-gfx] " Teres Alexis, Alan Previn 2023-05-27 0:52 ` [PATCH v3 6/7] drm/i915/mtl/huc: Use the media gt for the HuC getparam Daniele Ceraolo Spurio 2023-05-27 0:52 ` [Intel-gfx] " Daniele Ceraolo Spurio 2023-05-27 0:52 ` [PATCH v3 7/7] drm/i915/huc: define HuC FW version for MTL Daniele Ceraolo Spurio 2023-05-27 0:52 ` [Intel-gfx] " Daniele Ceraolo Spurio 2023-05-27 1:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: HuC loading and authentication for MTL (rev5) Patchwork 2023-05-27 1:22 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2023-05-27 1:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-05-28 1:07 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2023-05-31 9:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: HuC loading and authentication for MTL (rev6) Patchwork 2023-05-31 9:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2023-05-31 9:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230527005242.1346093-1-daniele.ceraolospurio@intel.com \ --to=daniele.ceraolospurio@intel.com \ --cc=John.C.Harrison@Intel.com \ --cc=alan.previn.teres.alexis@intel.com \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ --cc=tony.ye@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.