From: Like Xu <like.xu.linux@gmail.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v6 00/10] KVM: x86: Add AMD Guest PerfMonV2 PMU support
Date: Tue, 30 May 2023 14:04:13 +0800 [thread overview]
Message-ID: <20230530060423.32361-1-likexu@tencent.com> (raw)
Starting with Zen4, core PMU on AMD platforms such as Genoa and
Ryzen-7000 will support PerfMonV2, and it is also compatible with
legacy PERFCTR_CORE behavior and MSR addresses.
If you don't have access to the hardware specification, the commits
d6d0c7f681fd..7685665c390d for host perf can also bring a quick
overview. Its main change is the addition of three MSR's equivalent
to Intel V2, namely global_ctrl, global_status, global_status_clear.
It is worth noting that this feature is very attractive for reducing the
overhead of PMU virtualization, since multiple MSR accesses to multiple
counters will be replaced by a single access to the global register,
plus more accuracy gain when multiple guest counters are used.
All related testcases are passed on a Genoa box.
Please feel free to run more tests, add more or share comments.
Patch 0001-0007 could be applied earlier, which may help reduce
the burden on industrious reviewers.
Previous:
https://lore.kernel.org/kvm/20230214050757.9623-1-likexu@tencent.com/
V5 -> V6 Changelog:
- Introduce pmu_ops->MIN_NR_GP_COUNTERS and WARN_ON_ONCE; (Sean)
- Set MIN_NR_GP_COUNTERS = 2 instead of 1 for Intel Arch PMU;
Like Xu (10):
KVM: x86/pmu: Expose reprogram_counters() in pmu.h
KVM: x86/pmu: Return #GP if user sets the GLOBAL_STATUS reserved bits
KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic
KVM: x86: Explicitly zero cpuid "0xa" leaf when PMU is disabled
KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met
KVM: x86/pmu: Forget PERFCTR_CORE if the min num of counters isn't met
KVM: x86/pmu: Constrain the num of guest counters with kvm_pmu_cap
KVM: x86/cpuid: Add a KVM-only leaf to redirect AMD PerfMonV2 flag
KVM: x86/svm/pmu: Add AMD PerfMonV2 support
KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022
arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 -
arch/x86/kvm/cpuid.c | 30 +++++++++-
arch/x86/kvm/pmu.c | 83 +++++++++++++++++++++++---
arch/x86/kvm/pmu.h | 43 +++++++++++--
arch/x86/kvm/reverse_cpuid.h | 7 +++
arch/x86/kvm/svm/pmu.c | 68 +++++++++++++++------
arch/x86/kvm/svm/svm.c | 19 +++++-
arch/x86/kvm/vmx/pmu_intel.c | 33 +++-------
arch/x86/kvm/x86.c | 10 ++++
9 files changed, 230 insertions(+), 64 deletions(-)
base-commit: b9846a698c9aff4eb2214a06ac83638ad098f33f
--
2.40.1
next reply other threads:[~2023-05-30 6:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-30 6:04 Like Xu [this message]
2023-05-30 6:04 ` [PATCH v6 01/10] KVM: x86/pmu: Expose reprogram_counters() in pmu.h Like Xu
2023-05-30 6:04 ` [PATCH v6 02/10] KVM: x86/pmu: Return #GP if user sets the GLOBAL_STATUS reserved bits Like Xu
2023-06-02 21:59 ` Sean Christopherson
2023-05-30 6:04 ` [PATCH v6 03/10] KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic Like Xu
2023-06-02 23:23 ` Sean Christopherson
2023-05-30 6:04 ` [PATCH v6 04/10] KVM: x86: Explicitly zero cpuid "0xa" leaf when PMU is disabled Like Xu
2023-05-30 6:04 ` [PATCH v6 05/10] KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met Like Xu
2023-06-02 0:50 ` Sean Christopherson
2023-05-30 6:04 ` [PATCH v6 06/10] KVM: x86/pmu: Forget PERFCTR_CORE if the min " Like Xu
2023-05-30 6:04 ` [PATCH v6 07/10] KVM: x86/pmu: Constrain the num of guest counters with kvm_pmu_cap Like Xu
2023-05-30 6:04 ` [PATCH v6 08/10] KVM: x86/cpuid: Add a KVM-only leaf to redirect AMD PerfMonV2 flag Like Xu
2023-05-30 6:04 ` [PATCH v6 09/10] KVM: x86/svm/pmu: Add AMD PerfMonV2 support Like Xu
2023-05-30 6:04 ` [PATCH v6 10/10] KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022 Like Xu
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