[PATCH v2 4/8] KVM: selftests: Test Intel PMU architectural events on fixed counters

From: Jinrong Liang <ljr.kernel@gmail.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>, Like Xu <likexu@tencent.com>,
	David Matlack <dmatlack@google.com>,
	Aaron Lewis <aaronlewis@google.com>,
	Vitaly Kuznetsov <vkuznets@redhat.com>,
	Wanpeng Li <wanpengli@tencent.com>,
	Jinrong Liang <cloudliang@tencent.com>,
	kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 4/8] KVM: selftests: Test Intel PMU architectural events on fixed counters
Date: Tue, 30 May 2023 21:42:44 +0800	[thread overview]
Message-ID: <20230530134248.23998-5-cloudliang@tencent.com> (raw)
In-Reply-To: <20230530134248.23998-1-cloudliang@tencent.com>

From: Jinrong Liang <cloudliang@tencent.com>

Update test to cover Intel PMU architectural events on fixed counters.
Per Intel SDM, PMU users can also count architecture performance events
on fixed counters (specifically, FIXED_CTR0 for the retired instructions
and FIXED_CTR1 for cpu core cycles event). Therefore, if guest's CPUID
indicates that an architecture event is not available, the corresponding
fixed counter will also not count that event.

Co-developed-by: Like Xu <likexu@tencent.com>
Signed-off-by: Like Xu <likexu@tencent.com>
Signed-off-by: Jinrong Liang <cloudliang@tencent.com>
---
 .../kvm/x86_64/pmu_basic_functionality_test.c | 28 +++++++++++++++++--
 1 file changed, 25 insertions(+), 3 deletions(-)

diff --git a/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c b/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
index 1f100fd94d67..81029d05367a 100644
--- a/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
+++ b/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
@@ -47,7 +47,8 @@ static uint64_t run_vcpu(struct kvm_vcpu *vcpu, uint64_t *ucall_arg)
 }
 
 static void intel_guest_run_arch_event(uint8_t version, uint8_t max_gp_num,
-				       uint32_t ctr_base_msr, uint64_t evt_code)
+				       uint32_t ctr_base_msr, uint64_t evt_code,
+				       uint8_t max_fixed_num)
 {
 	uint32_t global_msr = MSR_CORE_PERF_GLOBAL_CTRL;
 	unsigned int i;
@@ -66,6 +67,27 @@ static void intel_guest_run_arch_event(uint8_t version, uint8_t max_gp_num,
 		GUEST_SYNC(_rdpmc(i));
 	}
 
+	/* No need to test independent arch events on fixed counters. */
+	if (version <= 1 || max_fixed_num <= 1)
+		goto done;
+
+	if (evt_code == evt_code_for_fixed_ctr(0))
+		i = 0;
+	else if (evt_code == evt_code_for_fixed_ctr(1))
+		i = 1;
+	else
+		goto done;
+
+	wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, 0);
+	wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * i));
+	wrmsr(global_msr, BIT_ULL(INTEL_PMC_IDX_FIXED + i));
+
+	__asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));
+
+	wrmsr(global_msr, 0);
+	GUEST_SYNC(_rdpmc(RDPMC_FIXED_BASE | i));
+
+done:
 	GUEST_DONE();
 }
 
@@ -90,8 +112,8 @@ static void test_arch_events_cpuid(struct kvm_vcpu *vcpu, uint8_t evt_vector,
 	is_supported = !(entry->ebx & BIT_ULL(idx)) &&
 		(((entry->eax & EVT_LEN_MASK) >> EVT_LEN_OFS_BIT) > idx);
 
-	vcpu_args_set(vcpu, 4, X86_INTEL_PMU_VERSION, X86_INTEL_MAX_GP_CTR_NUM,
-		      ctr_msr, arch_events[idx]);
+	vcpu_args_set(vcpu, 5, X86_INTEL_PMU_VERSION, X86_INTEL_MAX_GP_CTR_NUM,
+		      ctr_msr, arch_events[idx], X86_INTEL_MAX_FIXED_CTR_NUM);
 
 	while (run_vcpu(vcpu, &counter_val) != UCALL_DONE)
 		TEST_ASSERT(is_supported == !!counter_val,
-- 
2.31.1

