All of lore.kernel.org
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/42] xlnx-versal: Connect Xilinx VERSAL CANFD controllers
Date: Tue,  6 Jun 2023 10:47:38 +0100	[thread overview]
Message-ID: <20230606094814.3581397-7-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230606094814.3581397-1-peter.maydell@linaro.org>

From: Vikram Garhwal <vikram.garhwal@amd.com>

Connect CANFD0 and CANFD1 on the Versal-virt machine and update xlnx-versal-virt
document with CANFD command line examples.

Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/xlnx-versal-virt.rst | 31 ++++++++++++++++
 include/hw/arm/xlnx-versal.h         | 12 +++++++
 hw/arm/xlnx-versal-virt.c            | 53 ++++++++++++++++++++++++++++
 hw/arm/xlnx-versal.c                 | 37 +++++++++++++++++++
 4 files changed, 133 insertions(+)

diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst
index 92ad10d2da4..d2d1b266926 100644
--- a/docs/system/arm/xlnx-versal-virt.rst
+++ b/docs/system/arm/xlnx-versal-virt.rst
@@ -34,6 +34,7 @@ Implemented devices:
 - DDR memory
 - BBRAM (36 bytes of Battery-backed RAM)
 - eFUSE (3072 bytes of one-time field-programmable bit array)
+- 2 CANFDs
 
 QEMU does not yet model any other devices, including the PL and the AI Engine.
 
@@ -224,3 +225,33 @@ To use a different index value, N, from default of 1, add:
 
   Better yet, do not use actual product data when running guest image
   on this Xilinx Versal Virt board.
+
+Using CANFDs for Versal Virt
+""""""""""""""""""""""""""""
+Versal CANFD controller is developed based on SocketCAN and QEMU CAN bus
+implementation. Bus connection and socketCAN connection for each CAN module
+can be set through command lines.
+
+To connect both CANFD0 and CANFD1 on the same bus:
+
+.. code-block:: bash
+
+    -object can-bus,id=canbus -machine canbus0=canbus -machine canbus1=canbus
+
+To connect CANFD0 and CANFD1 to separate buses:
+
+.. code-block:: bash
+
+    -object can-bus,id=canbus0 -object can-bus,id=canbus1 \
+    -machine canbus0=canbus0 -machine canbus1=canbus1
+
+The SocketCAN interface can connect to a Physical or a Virtual CAN interfaces on
+the host machine. Please check this document to learn about CAN interface on
+Linux: docs/system/devices/can.rst
+
+To connect CANFD0 and CANFD1 to host machine's CAN interface can0:
+
+.. code-block:: bash
+
+    -object can-bus,id=canbus -machine canbus0=canbus -machine canbus1=canbus
+    -object can-host-socketcan,id=canhost0,if=can0,canbus=canbus
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index b6786e9832d..39ee31185c3 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -31,6 +31,7 @@
 #include "hw/dma/xlnx_csu_dma.h"
 #include "hw/misc/xlnx-versal-crl.h"
 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
+#include "hw/net/xlnx-versal-canfd.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
 OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
@@ -43,6 +44,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
 #define XLNX_VERSAL_NR_SDS     2
 #define XLNX_VERSAL_NR_XRAM    4
 #define XLNX_VERSAL_NR_IRQS    192
+#define XLNX_VERSAL_NR_CANFD   2
+#define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000)
 
 struct Versal {
     /*< private >*/
@@ -73,6 +76,8 @@ struct Versal {
             CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
             XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
             VersalUsb2 usb;
+            CanBusState *canbus[XLNX_VERSAL_NR_CANFD];
+            XlnxVersalCANFDState canfd[XLNX_VERSAL_NR_CANFD];
         } iou;
 
         /* Real-time Processing Unit.  */
@@ -133,6 +138,8 @@ struct Versal {
 #define VERSAL_CRL_IRQ             10
 #define VERSAL_UART0_IRQ_0         18
 #define VERSAL_UART1_IRQ_0         19
+#define VERSAL_CANFD0_IRQ_0        20
+#define VERSAL_CANFD1_IRQ_0        21
 #define VERSAL_USB0_IRQ_0          22
 #define VERSAL_GEM0_IRQ_0          56
 #define VERSAL_GEM0_WAKE_IRQ_0     57
@@ -163,6 +170,11 @@ struct Versal {
 #define MM_UART1                    0xff010000U
 #define MM_UART1_SIZE               0x10000
 
+#define MM_CANFD0                   0xff060000U
+#define MM_CANFD0_SIZE              0x10000
+#define MM_CANFD1                   0xff070000U
+#define MM_CANFD1_SIZE              0x10000
+
 #define MM_GEM0                     0xff0c0000U
 #define MM_GEM0_SIZE                0x10000
 #define MM_GEM1                     0xff0d0000U
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 668a9d65a43..1ee2b8697fe 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -40,9 +40,11 @@ struct VersalVirt {
         uint32_t clk_25Mhz;
         uint32_t usb;
         uint32_t dwc;
+        uint32_t canfd[2];
     } phandle;
     struct arm_boot_info binfo;
 
+    CanBusState *canbus[XLNX_VERSAL_NR_CANFD];
     struct {
         bool secure;
     } cfg;
@@ -235,6 +237,38 @@ static void fdt_add_uart_nodes(VersalVirt *s)
     }
 }
 
+static void fdt_add_canfd_nodes(VersalVirt *s)
+{
+    uint64_t addrs[] = { MM_CANFD1, MM_CANFD0 };
+    uint32_t size[] = { MM_CANFD1_SIZE, MM_CANFD0_SIZE };
+    unsigned int irqs[] = { VERSAL_CANFD1_IRQ_0, VERSAL_CANFD0_IRQ_0 };
+    const char clocknames[] = "can_clk\0s_axi_aclk";
+    int i;
+
+    /* Create and connect CANFD0 and CANFD1 nodes to canbus0. */
+    for (i = 0; i < ARRAY_SIZE(addrs); i++) {
+        char *name = g_strdup_printf("/canfd@%" PRIx64, addrs[i]);
+        qemu_fdt_add_subnode(s->fdt, name);
+
+        qemu_fdt_setprop_cell(s->fdt, name, "rx-fifo-depth", 0x40);
+        qemu_fdt_setprop_cell(s->fdt, name, "tx-mailbox-count", 0x20);
+
+        qemu_fdt_setprop_cells(s->fdt, name, "clocks",
+                               s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
+        qemu_fdt_setprop(s->fdt, name, "clock-names",
+                         clocknames, sizeof(clocknames));
+        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+                               GIC_FDT_IRQ_TYPE_SPI, irqs[i],
+                               GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+                                     2, addrs[i], 2, size[i]);
+        qemu_fdt_setprop_string(s->fdt, name, "compatible",
+                                "xlnx,canfd-2.0");
+
+        g_free(name);
+    }
+}
+
 static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname,
                                      uint32_t phandle)
 {
@@ -639,12 +673,17 @@ static void versal_virt_init(MachineState *machine)
                             TYPE_XLNX_VERSAL);
     object_property_set_link(OBJECT(&s->soc), "ddr", OBJECT(machine->ram),
                              &error_abort);
+    object_property_set_link(OBJECT(&s->soc), "canbus0", OBJECT(s->canbus[0]),
+                             &error_abort);
+    object_property_set_link(OBJECT(&s->soc), "canbus1", OBJECT(s->canbus[1]),
+                             &error_abort);
     sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
 
     fdt_create(s);
     create_virtio_regions(s);
     fdt_add_gem_nodes(s);
     fdt_add_uart_nodes(s);
+    fdt_add_canfd_nodes(s);
     fdt_add_gic_nodes(s);
     fdt_add_timer_nodes(s);
     fdt_add_zdma_nodes(s);
@@ -712,6 +751,20 @@ static void versal_virt_init(MachineState *machine)
 
 static void versal_virt_machine_instance_init(Object *obj)
 {
+    VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(obj);
+
+    /*
+     * User can set canbus0 and canbus1 properties to can-bus object and connect
+     * to socketcan(optional) interface via command line.
+     */
+    object_property_add_link(obj, "canbus0", TYPE_CAN_BUS,
+                             (Object **)&s->canbus[0],
+                             object_property_allow_set_link,
+                             0);
+    object_property_add_link(obj, "canbus1", TYPE_CAN_BUS,
+                             (Object **)&s->canbus[1],
+                             object_property_allow_set_link,
+                             0);
 }
 
 static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 69b1b99e937..1594dd6c5c5 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -184,6 +184,38 @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)
     }
 }
 
+static void versal_create_canfds(Versal *s, qemu_irq *pic)
+{
+    int i;
+    uint32_t irqs[] = { VERSAL_CANFD0_IRQ_0, VERSAL_CANFD1_IRQ_0};
+    uint64_t addrs[] = { MM_CANFD0, MM_CANFD1 };
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.canfd); i++) {
+        char *name = g_strdup_printf("canfd%d", i);
+        SysBusDevice *sbd;
+        MemoryRegion *mr;
+
+        object_initialize_child(OBJECT(s), name, &s->lpd.iou.canfd[i],
+                                TYPE_XILINX_CANFD);
+        sbd = SYS_BUS_DEVICE(&s->lpd.iou.canfd[i]);
+
+        object_property_set_int(OBJECT(&s->lpd.iou.canfd[i]), "ext_clk_freq",
+                                XLNX_VERSAL_CANFD_REF_CLK , &error_abort);
+
+        object_property_set_link(OBJECT(&s->lpd.iou.canfd[i]), "canfdbus",
+                                 OBJECT(s->lpd.iou.canbus[i]),
+                                 &error_abort);
+
+        sysbus_realize(sbd, &error_fatal);
+
+        mr = sysbus_mmio_get_region(sbd, 0);
+        memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
+
+        sysbus_connect_irq(sbd, 0, pic[irqs[i]]);
+        g_free(name);
+    }
+}
+
 static void versal_create_usbs(Versal *s, qemu_irq *pic)
 {
     DeviceState *dev;
@@ -718,6 +750,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
     versal_create_apu_gic(s, pic);
     versal_create_rpu_cpus(s);
     versal_create_uarts(s, pic);
+    versal_create_canfds(s, pic);
     versal_create_usbs(s, pic);
     versal_create_gems(s, pic);
     versal_create_admas(s, pic);
@@ -757,6 +790,10 @@ static void versal_init(Object *obj)
 static Property versal_properties[] = {
     DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION,
                      MemoryRegion *),
+    DEFINE_PROP_LINK("canbus0", Versal, lpd.iou.canbus[0],
+                      TYPE_CAN_BUS, CanBusState *),
+    DEFINE_PROP_LINK("canbus1", Versal, lpd.iou.canbus[1],
+                      TYPE_CAN_BUS, CanBusState *),
     DEFINE_PROP_END_OF_LIST()
 };
 
-- 
2.34.1



  parent reply	other threads:[~2023-06-06  9:49 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-06  9:47 [PULL 00/42] target-arm queue Peter Maydell
2023-06-06  9:47 ` [PULL 01/42] arm: move KVM breakpoints helpers Peter Maydell
2023-06-06  9:47 ` [PULL 02/42] hvf: handle access for more registers Peter Maydell
2023-06-06  9:47 ` [PULL 03/42] hvf: add breakpoint handlers Peter Maydell
2023-06-06  9:47 ` [PULL 04/42] hvf: add guest debugging handlers for Apple Silicon hosts Peter Maydell
2023-06-06  9:47 ` [PULL 05/42] hw/net/can: Introduce Xilinx Versal CANFD controller Peter Maydell
2023-06-06  9:47 ` Peter Maydell [this message]
2023-06-06  9:47 ` [PULL 07/42] MAINTAINERS: Include canfd tests under Xilinx CAN Peter Maydell
2023-06-06  9:47 ` [PULL 08/42] tests/qtest: Introduce tests for Xilinx VERSAL CANFD controller Peter Maydell
2023-06-06  9:47 ` [PULL 09/42] hw: arm: Add bananapi M2-Ultra and allwinner-r40 support Peter Maydell
2023-06-06  9:47 ` [PULL 10/42] hw/arm/allwinner-r40: add Clock Control Unit Peter Maydell
2023-06-06  9:47 ` [PULL 11/42] hw: allwinner-r40: Complete uart devices Peter Maydell
2023-06-06  9:47 ` [PULL 12/42] hw: arm: allwinner-r40: Add i2c0 device Peter Maydell
2023-06-06  9:47 ` [PULL 13/42] hw/misc: Rename axp209 to axp22x and add support AXP221 PMU Peter Maydell
2023-06-06  9:47 ` [PULL 14/42] hw/arm/allwinner-r40: add SDRAM controller device Peter Maydell
2023-06-06  9:47 ` [PULL 15/42] hw: sd: allwinner-sdhost: Add sun50i-a64 SoC support Peter Maydell
2023-06-06  9:47 ` [PULL 16/42] hw: arm: allwinner-r40: Add emac and gmac support Peter Maydell
2023-06-06  9:47 ` [PULL 17/42] hw: arm: allwinner-sramc: Add SRAM Controller support for R40 Peter Maydell
2023-06-06  9:47 ` [PULL 18/42] tests: avocado: boot_linux_console: Add test case for bpim2u Peter Maydell
2023-06-29 11:35   ` Thomas Huth
2023-06-30  6:15     ` qianfan
2023-06-30  6:22       ` qianfan
2023-06-30  7:27       ` Thomas Huth
2023-06-30  8:45         ` qianfan
2023-06-30  8:53           ` Thomas Huth
2023-06-30  9:04             ` qianfan
2023-06-30 15:45               ` Thomas Huth
2023-07-03 11:14                 ` Peter Maydell
2023-06-06  9:47 ` [PULL 19/42] docs: system: arm: Introduce bananapi_m2u Peter Maydell
2023-06-06  9:47 ` [PULL 20/42] target/arm: Add commentary for CPUARMState.exclusive_high Peter Maydell
2023-06-06  9:47 ` [PULL 21/42] target/arm: Add feature test for FEAT_LSE2 Peter Maydell
2023-06-06  9:47 ` [PULL 22/42] target/arm: Introduce finalize_memop_{atom,pair} Peter Maydell
2023-06-06  9:47 ` [PULL 23/42] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP Peter Maydell
2023-06-06  9:47 ` [PULL 24/42] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld} Peter Maydell
2023-06-06  9:47 ` [PULL 25/42] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G Peter Maydell
2023-06-06  9:47 ` [PULL 26/42] target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r Peter Maydell
2023-06-12 15:20   ` Jonathan Cameron via
2023-06-12 18:40     ` Mark Cave-Ayland
2023-06-13  9:26       ` Jonathan Cameron via
2023-06-06  9:47 ` [PULL 27/42] target/arm: Sink gen_mte_check1 into load/store_exclusive Peter Maydell
2023-06-06  9:48 ` [PULL 28/42] target/arm: Load/store integer pair with one tcg operation Peter Maydell
2023-06-06  9:48 ` [PULL 29/42] target/arm: Hoist finalize_memop out of do_gpr_{ld, st} Peter Maydell
2023-06-06  9:48 ` [PULL 30/42] target/arm: Hoist finalize_memop out of do_fp_{ld, st} Peter Maydell
2023-06-06  9:48 ` [PULL 31/42] target/arm: Pass memop to gen_mte_check1* Peter Maydell
2023-06-06  9:48 ` [PULL 32/42] target/arm: Pass single_memop to gen_mte_checkN Peter Maydell
2023-06-06  9:48 ` [PULL 33/42] target/arm: Check alignment in helper_mte_check Peter Maydell
2023-06-06  9:48 ` [PULL 34/42] target/arm: Add SCTLR.nAA to TBFLAG_A64 Peter Maydell
2023-06-06  9:48 ` [PULL 35/42] target/arm: Relax ordered/atomic alignment checks for LSE2 Peter Maydell
2023-06-06  9:48 ` [PULL 36/42] target/arm: Move mte check for store-exclusive Peter Maydell
2023-06-06  9:48 ` [PULL 37/42] tests/tcg/aarch64: Use stz2g in mte-7.c Peter Maydell
2023-06-06  9:48 ` [PULL 38/42] tests/tcg/multiarch: Adjust sigbus.c Peter Maydell
2023-06-06  9:48 ` [PULL 39/42] target/arm: Enable FEAT_LSE2 for -cpu max Peter Maydell
2023-06-06  9:48 ` [PULL 40/42] target/arm: allow DC CVA[D]P in user mode emulation Peter Maydell
2023-06-06  9:48 ` [PULL 41/42] tests/tcg/aarch64: add DC CVA[D]P tests Peter Maydell
2023-06-06  9:48 ` [PULL 42/42] target/arm: trap DCC access in user mode emulation Peter Maydell
2023-06-06 21:36 ` [PULL 00/42] target-arm queue Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230606094814.3581397-7-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.