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From: Conor Dooley <conor@kernel.org>
To: palmer@dabbelt.com
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v1 4/6] dt-bindings: riscv: cpus: permit operating-points-v2
Date: Sat, 10 Jun 2023 18:24:51 +0100	[thread overview]
Message-ID: <20230610-jacket-king-486b50a4e01d@spud> (raw)
In-Reply-To: <20230610-snaking-version-81ae5abb7573@spud>

From: Conor Dooley <conor.dooley@microchip.com>

To allow setting "unevaluatedProperties: false" for cpus.yaml, permit
the operating points property for RISC-V cpu nodes.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 9bf2b72a9460..00d1e273f1a9 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -108,6 +108,7 @@ properties:
   # RISC-V has multiple properties for cache op block sizes as the sizes
   # differ between individual CBO extensions
   cache-op-block-size: false
+  operating-points-v2: true
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false
 
-- 
2.39.2


WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: palmer@dabbelt.com
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v1 4/6] dt-bindings: riscv: cpus: permit operating-points-v2
Date: Sat, 10 Jun 2023 18:24:51 +0100	[thread overview]
Message-ID: <20230610-jacket-king-486b50a4e01d@spud> (raw)
In-Reply-To: <20230610-snaking-version-81ae5abb7573@spud>

From: Conor Dooley <conor.dooley@microchip.com>

To allow setting "unevaluatedProperties: false" for cpus.yaml, permit
the operating points property for RISC-V cpu nodes.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 9bf2b72a9460..00d1e273f1a9 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -108,6 +108,7 @@ properties:
   # RISC-V has multiple properties for cache op block sizes as the sizes
   # differ between individual CBO extensions
   cache-op-block-size: false
+  operating-points-v2: true
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false
 
-- 
2.39.2


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http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2023-06-10 17:25 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-10 17:24 [PATCH v1 0/6] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false Conor Dooley
2023-06-10 17:24 ` Conor Dooley
2023-06-10 17:24 ` [PATCH v1 1/6] dt-bindings: riscv: cpus: add a ref the common cpu schema Conor Dooley
2023-06-10 17:24   ` Conor Dooley
2023-06-10 17:24 ` [PATCH v1 2/6] dt-bindings: riscv: cpus: allow clocks property Conor Dooley
2023-06-10 17:24   ` Conor Dooley
2023-06-10 17:24 ` [PATCH v1 3/6] dt-bindings: riscv: cpus: add a ref to thermal-cooling-cells Conor Dooley
2023-06-10 17:24   ` Conor Dooley
2023-06-10 17:24 ` Conor Dooley [this message]
2023-06-10 17:24   ` [PATCH v1 4/6] dt-bindings: riscv: cpus: permit operating-points-v2 Conor Dooley
2023-06-10 17:24 ` [PATCH v1 5/6] dt-bindings: riscv: cpus: document cpu-supply Conor Dooley
2023-06-10 17:24   ` Conor Dooley
2023-06-10 17:24 ` [PATCH v1 6/6] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false Conor Dooley
2023-06-10 17:24   ` Conor Dooley
2023-06-15 17:47 ` [PATCH v1 0/6] " Rob Herring
2023-06-15 17:47   ` Rob Herring
2023-06-15 21:46   ` Conor Dooley
2023-06-15 21:46     ` Conor Dooley

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