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From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH 1/3] riscv: errata: thead: only set cbom size & noncoherent during boot
Date: Thu, 15 Jun 2023 00:55:02 +0800	[thread overview]
Message-ID: <20230614165504.532-2-jszhang@kernel.org> (raw)
In-Reply-To: <20230614165504.532-1-jszhang@kernel.org>

The CBOM size and whether the HW is noncoherent is known and
determined during booting and won't change after that.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/errata/thead/errata.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index c259dc925ec1..be84b14f0118 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -45,8 +45,11 @@ static bool errata_probe_cmo(unsigned int stage,
 	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
 		return false;
 
-	riscv_cbom_block_size = L1_CACHE_BYTES;
-	riscv_noncoherent_supported();
+	if (stage == RISCV_ALTERNATIVES_BOOT) {
+		riscv_cbom_block_size = L1_CACHE_BYTES;
+		riscv_noncoherent_supported();
+	}
+
 	return true;
 }
 
-- 
2.40.1


WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH 1/3] riscv: errata: thead: only set cbom size & noncoherent during boot
Date: Thu, 15 Jun 2023 00:55:02 +0800	[thread overview]
Message-ID: <20230614165504.532-2-jszhang@kernel.org> (raw)
In-Reply-To: <20230614165504.532-1-jszhang@kernel.org>

The CBOM size and whether the HW is noncoherent is known and
determined during booting and won't change after that.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/errata/thead/errata.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index c259dc925ec1..be84b14f0118 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -45,8 +45,11 @@ static bool errata_probe_cmo(unsigned int stage,
 	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
 		return false;
 
-	riscv_cbom_block_size = L1_CACHE_BYTES;
-	riscv_noncoherent_supported();
+	if (stage == RISCV_ALTERNATIVES_BOOT) {
+		riscv_cbom_block_size = L1_CACHE_BYTES;
+		riscv_noncoherent_supported();
+	}
+
 	return true;
 }
 
-- 
2.40.1


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  reply	other threads:[~2023-06-14 17:06 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-14 16:55 [PATCH 0/3] riscv: some CMO alternative related clean up Jisheng Zhang
2023-06-14 16:55 ` Jisheng Zhang
2023-06-14 16:55 ` Jisheng Zhang [this message]
2023-06-14 16:55   ` [PATCH 1/3] riscv: errata: thead: only set cbom size & noncoherent during boot Jisheng Zhang
2023-06-14 16:55 ` [PATCH 2/3] riscv: mm: mark CBO relate initialization funcs as __init Jisheng Zhang
2023-06-14 16:55   ` Jisheng Zhang
2023-06-14 16:55 ` [PATCH 3/3] riscv: mm: mark noncoherent_supported as __ro_after_init Jisheng Zhang
2023-06-14 16:55   ` Jisheng Zhang
2023-07-07 15:10 ` [PATCH 0/3] riscv: some CMO alternative related clean up patchwork-bot+linux-riscv
2023-07-07 15:10   ` patchwork-bot+linux-riscv

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