From: Heiko Stuebner <heiko@sntech.de> To: palmer@dabbelt.com, paul.walmsley@sifive.com Cc: linux-riscv@lists.infradead.org, samuel@sholland.org, guoren@kernel.org, christoph.muellner@vrull.eu, heiko@sntech.de, conor.dooley@microchip.com, linux-kernel@vger.kernel.org, Heiko Stuebner <heiko.stuebner@vrull.eu> Subject: [PATCH v2 2/3] RISC-V: move vector-available status into a dedicated variable Date: Fri, 23 Jun 2023 01:13:04 +0200 [thread overview] Message-ID: <20230622231305.631331-3-heiko@sntech.de> (raw) In-Reply-To: <20230622231305.631331-1-heiko@sntech.de> From: Heiko Stuebner <heiko.stuebner@vrull.eu> There is at least one core implementing the wrong vector specification, which cannot claim to implement the v extension but still is able to do vectors similar to v. To not hack around this by claiming to do v, move the has_vector() return to act similar to riscv_noncoherent_supported() and move to a separate variable that can be set for example from errata code. Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> --- arch/riscv/include/asm/vector.h | 5 ++++- arch/riscv/kernel/setup.c | 6 ++++++ arch/riscv/kernel/vector.c | 8 ++++++++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 04c0b07bf6cd..315c96d2b4d0 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -19,13 +19,16 @@ #include <asm/csr.h> #include <asm/asm.h> +extern bool riscv_v_supported; +void riscv_vector_supported(void); + extern unsigned long riscv_v_vsize; int riscv_v_setup_vsize(void); bool riscv_v_first_use_handler(struct pt_regs *regs); static __always_inline bool has_vector(void) { - return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); + return riscv_v_supported; } static inline void __riscv_v_vstate_clean(struct pt_regs *regs) diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 971fe776e2f8..952dfb90525e 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -36,6 +36,7 @@ #include <asm/thread_info.h> #include <asm/kasan.h> #include <asm/efi.h> +#include <asm/vector.h> #include "head.h" @@ -308,6 +309,11 @@ void __init setup_arch(char **cmdline_p) riscv_fill_hwcap(); init_rt_signal_env(); apply_boot_alternatives(); + + if (IS_ENABLED(CONFIG_RISCV_ISA_V) && + riscv_isa_extension_available(NULL, v)) + riscv_vector_supported(); + if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && riscv_isa_extension_available(NULL, ZICBOM)) riscv_noncoherent_supported(); diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index f9c8e19ab301..74178fb71805 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -22,6 +22,9 @@ static bool riscv_v_implicit_uacc = IS_ENABLED(CONFIG_RISCV_ISA_V_DEFAULT_ENABLE); +bool riscv_v_supported; +EXPORT_SYMBOL_GPL(riscv_v_supported); + unsigned long riscv_v_vsize __read_mostly; EXPORT_SYMBOL_GPL(riscv_v_vsize); @@ -274,3 +277,8 @@ static int riscv_v_init(void) return riscv_v_sysctl_init(); } core_initcall(riscv_v_init); + +void riscv_vector_supported(void) +{ + riscv_v_supported = true; +} -- 2.39.2
WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de> To: palmer@dabbelt.com, paul.walmsley@sifive.com Cc: linux-riscv@lists.infradead.org, samuel@sholland.org, guoren@kernel.org, christoph.muellner@vrull.eu, heiko@sntech.de, conor.dooley@microchip.com, linux-kernel@vger.kernel.org, Heiko Stuebner <heiko.stuebner@vrull.eu> Subject: [PATCH v2 2/3] RISC-V: move vector-available status into a dedicated variable Date: Fri, 23 Jun 2023 01:13:04 +0200 [thread overview] Message-ID: <20230622231305.631331-3-heiko@sntech.de> (raw) In-Reply-To: <20230622231305.631331-1-heiko@sntech.de> From: Heiko Stuebner <heiko.stuebner@vrull.eu> There is at least one core implementing the wrong vector specification, which cannot claim to implement the v extension but still is able to do vectors similar to v. To not hack around this by claiming to do v, move the has_vector() return to act similar to riscv_noncoherent_supported() and move to a separate variable that can be set for example from errata code. Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> --- arch/riscv/include/asm/vector.h | 5 ++++- arch/riscv/kernel/setup.c | 6 ++++++ arch/riscv/kernel/vector.c | 8 ++++++++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 04c0b07bf6cd..315c96d2b4d0 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -19,13 +19,16 @@ #include <asm/csr.h> #include <asm/asm.h> +extern bool riscv_v_supported; +void riscv_vector_supported(void); + extern unsigned long riscv_v_vsize; int riscv_v_setup_vsize(void); bool riscv_v_first_use_handler(struct pt_regs *regs); static __always_inline bool has_vector(void) { - return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); + return riscv_v_supported; } static inline void __riscv_v_vstate_clean(struct pt_regs *regs) diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 971fe776e2f8..952dfb90525e 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -36,6 +36,7 @@ #include <asm/thread_info.h> #include <asm/kasan.h> #include <asm/efi.h> +#include <asm/vector.h> #include "head.h" @@ -308,6 +309,11 @@ void __init setup_arch(char **cmdline_p) riscv_fill_hwcap(); init_rt_signal_env(); apply_boot_alternatives(); + + if (IS_ENABLED(CONFIG_RISCV_ISA_V) && + riscv_isa_extension_available(NULL, v)) + riscv_vector_supported(); + if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && riscv_isa_extension_available(NULL, ZICBOM)) riscv_noncoherent_supported(); diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index f9c8e19ab301..74178fb71805 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -22,6 +22,9 @@ static bool riscv_v_implicit_uacc = IS_ENABLED(CONFIG_RISCV_ISA_V_DEFAULT_ENABLE); +bool riscv_v_supported; +EXPORT_SYMBOL_GPL(riscv_v_supported); + unsigned long riscv_v_vsize __read_mostly; EXPORT_SYMBOL_GPL(riscv_v_vsize); @@ -274,3 +277,8 @@ static int riscv_v_init(void) return riscv_v_sysctl_init(); } core_initcall(riscv_v_init); + +void riscv_vector_supported(void) +{ + riscv_v_supported = true; +} -- 2.39.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-06-22 23:13 UTC|newest] Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-06-22 23:13 [PATCH v2 0/2] RISC-V: T-Head vector handling Heiko Stuebner 2023-06-22 23:13 ` Heiko Stuebner 2023-06-22 23:13 ` [PATCH v2 1/3] RISC-V: define the elements of the VCSR vector CSR Heiko Stuebner 2023-06-22 23:13 ` Heiko Stuebner 2023-06-22 23:13 ` Heiko Stuebner [this message] 2023-06-22 23:13 ` [PATCH v2 2/3] RISC-V: move vector-available status into a dedicated variable Heiko Stuebner 2023-06-23 9:19 ` Conor Dooley 2023-06-23 9:19 ` Conor Dooley 2023-06-23 13:47 ` kernel test robot 2023-06-23 13:47 ` kernel test robot 2023-06-22 23:13 ` [PATCH v2 3/3] RISC-V: add T-Head vector errata handling Heiko Stuebner 2023-06-22 23:13 ` Heiko Stuebner 2023-06-23 3:11 ` kernel test robot 2023-06-23 3:11 ` kernel test robot 2023-06-23 9:49 ` Conor Dooley 2023-06-23 9:49 ` Conor Dooley 2023-06-23 10:40 ` Heiko Stübner 2023-06-23 10:40 ` Heiko Stübner 2023-06-23 11:44 ` Conor Dooley 2023-06-23 11:44 ` Conor Dooley 2023-06-24 5:18 ` Stefan O'Rear 2023-06-24 5:18 ` Stefan O'Rear 2023-06-24 10:59 ` Andrew Jones 2023-06-24 10:59 ` Andrew Jones 2023-06-28 16:07 ` Andy Chiu 2023-06-28 16:07 ` Andy Chiu 2023-06-23 13:47 ` kernel test robot 2023-06-23 13:47 ` kernel test robot 2023-06-27 15:21 ` Rémi Denis-Courmont 2023-06-27 16:12 ` Conor Dooley 2023-06-28 14:23 ` Palmer Dabbelt 2023-06-29 16:06 ` Rémi Denis-Courmont 2023-06-29 16:06 ` Rémi Denis-Courmont
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230622231305.631331-3-heiko@sntech.de \ --to=heiko@sntech.de \ --cc=christoph.muellner@vrull.eu \ --cc=conor.dooley@microchip.com \ --cc=guoren@kernel.org \ --cc=heiko.stuebner@vrull.eu \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=samuel@sholland.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.