From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Subject: [PATCH 5.10.y-cip v2 03/13] clk: renesas: r9a07g044: Add MTU3a clock and reset entry
Date: Thu, 20 Jul 2023 11:03:40 +0100 [thread overview]
Message-ID: <20230720100350.247386-4-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20230720100350.247386-1-biju.das.jz@bp.renesas.com>
commit 576d6b40dcceade7d77e88f63e621349c6937bc3 upstream.
Add MTU3a clock and reset entry to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20221005111855.553436-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index b31201c7ca7b..29b2a69d58d2 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -151,7 +151,7 @@ static const struct {
};
static const struct {
- struct rzg2l_mod_clk common[62];
+ struct rzg2l_mod_clk common[63];
#ifdef CONFIG_CLK_R9A07G054
struct rzg2l_mod_clk drp[0];
#endif
@@ -173,6 +173,8 @@ static const struct {
0x534, 1),
DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
0x534, 2),
+ DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
+ 0x538, 0),
DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
0x548, 0),
DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
@@ -297,6 +299,7 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
+ DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
--
2.25.1
next prev parent reply other threads:[~2023-07-20 10:04 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 10:03 [PATCH 5.10.y-cip v2 00/13] Add RZ/{G2L,G2LC,V2L} MTU3 support Biju Das
2023-07-20 10:03 ` [PATCH 5.10.y-cip v2 01/13] arm64: dts: renesas: rzg2l-smarc: Use proper bool operator Biju Das
2023-07-20 10:03 ` [PATCH 5.10.y-cip v2 02/13] arm64: dts: renesas: rzg2lc-smarc: Include SoM DTSI into board DTS Biju Das
2023-07-20 10:03 ` Biju Das [this message]
2023-07-20 10:03 ` [PATCH 5.10.y-cip v2 04/13] dt-bindings: timer: Document RZ/G2L MTU3a bindings Biju Das
2023-07-20 10:03 ` [PATCH 5.10.y-cip v2 05/13] mfd: Add Renesas RZ/G2L MTU3a core driver Biju Das
2023-07-20 10:03 ` [PATCH 5.10.y-cip v2 06/13] arm64: defconfig: Enable Renesas MTU3a counter config Biju Das
2023-07-20 10:03 ` [PATCH 5.10.y-cip v2 07/13] pwm: Add a device-managed function to add PWM chips Biju Das
2023-07-20 10:03 ` [PATCH 5.10.y-cip v2 08/13] pwm: Add Renesas RZ/G2L MTU3a PWM driver Biju Das
2023-07-20 10:03 ` [PATCH 5.10.y-cip v2 09/13] arm64: dts: renesas: r9a07g044: Add MTU3a node Biju Das
2023-07-20 10:03 ` [PATCH 5.10.y-cip v2 10/13] arm64: dts: renesas: r9a07g054: " Biju Das
2023-07-20 10:03 ` [PATCH 5.10.y-cip v2 11/13] arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3 Biju Das
2023-07-20 10:03 ` [PATCH 5.10.y-cip v2 12/13] arm64: dts: renesas: rzg2lc-smarc: " Biju Das
2023-07-20 10:03 ` [PATCH 5.10.y-cip v2 13/13] arm64: defconfig: Enable Renesas MTU3a PWM config Biju Das
2023-07-20 17:53 ` [PATCH 5.10.y-cip v2 00/13] Add RZ/{G2L,G2LC,V2L} MTU3 support Pavel Machek
2023-08-09 1:58 ` [cip-dev] " nobuhiro1.iwamatsu
2023-08-09 6:28 ` Biju Das
2023-08-09 6:33 ` nobuhiro1.iwamatsu
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