From: Alexandre Ghiti <alexghiti@rivosinc.com> To: "Paul Walmsley" <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Björn Töpel" <bjorn@rivosinc.com>, "Alexandre Ghiti" <alexghiti@rivosinc.com>, "Guo Ren" <guoren@kernel.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH -fixes] riscv: Implement flush_cache_vmap() Date: Tue, 25 Jul 2023 15:22:46 +0200 [thread overview] Message-ID: <20230725132246.817726-1-alexghiti@rivosinc.com> (raw) The RISC-V kernel needs a sfence.vma after a page table modification: we used to rely on the vmalloc fault handling to emit an sfence.vma, but commit 7d3332be011e ("riscv: mm: Pre-allocate PGD entries for vmalloc/modules area") got rid of this path for 64-bit kernels, so now we need to explicitly emit a sfence.vma in flush_cache_vmap(). Note that we don't need to implement flush_cache_vunmap() as the generic code should emit a flush tlb after unmapping a vmalloc region. Fixes: 7d3332be011e ("riscv: mm: Pre-allocate PGD entries for vmalloc/modules area") Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> --- arch/riscv/include/asm/cacheflush.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 8091b8bf4883..b93ffddf8a61 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -37,6 +37,10 @@ static inline void flush_dcache_page(struct page *page) #define flush_icache_user_page(vma, pg, addr, len) \ flush_icache_mm(vma->vm_mm, 0) +#ifdef CONFIG_64BIT +#define flush_cache_vmap(start, end) flush_tlb_kernel_range(start, end) +#endif + #ifndef CONFIG_SMP #define flush_icache_all() local_flush_icache_all() -- 2.39.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
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From: Alexandre Ghiti <alexghiti@rivosinc.com> To: "Paul Walmsley" <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Björn Töpel" <bjorn@rivosinc.com>, "Alexandre Ghiti" <alexghiti@rivosinc.com>, "Guo Ren" <guoren@kernel.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH -fixes] riscv: Implement flush_cache_vmap() Date: Tue, 25 Jul 2023 15:22:46 +0200 [thread overview] Message-ID: <20230725132246.817726-1-alexghiti@rivosinc.com> (raw) The RISC-V kernel needs a sfence.vma after a page table modification: we used to rely on the vmalloc fault handling to emit an sfence.vma, but commit 7d3332be011e ("riscv: mm: Pre-allocate PGD entries for vmalloc/modules area") got rid of this path for 64-bit kernels, so now we need to explicitly emit a sfence.vma in flush_cache_vmap(). Note that we don't need to implement flush_cache_vunmap() as the generic code should emit a flush tlb after unmapping a vmalloc region. Fixes: 7d3332be011e ("riscv: mm: Pre-allocate PGD entries for vmalloc/modules area") Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> --- arch/riscv/include/asm/cacheflush.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 8091b8bf4883..b93ffddf8a61 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -37,6 +37,10 @@ static inline void flush_dcache_page(struct page *page) #define flush_icache_user_page(vma, pg, addr, len) \ flush_icache_mm(vma->vm_mm, 0) +#ifdef CONFIG_64BIT +#define flush_cache_vmap(start, end) flush_tlb_kernel_range(start, end) +#endif + #ifndef CONFIG_SMP #define flush_icache_all() local_flush_icache_all() -- 2.39.2
next reply other threads:[~2023-07-25 13:23 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-07-25 13:22 Alexandre Ghiti [this message] 2023-07-25 13:22 ` [PATCH -fixes] riscv: Implement flush_cache_vmap() Alexandre Ghiti 2023-07-30 5:08 ` Guo Ren 2023-07-30 5:08 ` Guo Ren 2023-08-03 9:14 ` dylan 2023-08-03 9:14 ` dylan 2023-08-03 9:24 ` Conor Dooley 2023-08-03 9:24 ` Conor Dooley 2023-08-03 9:48 ` Alexandre Ghiti 2023-08-03 9:48 ` Alexandre Ghiti 2023-08-03 9:58 ` Alexandre Ghiti 2023-08-03 9:58 ` Alexandre Ghiti 2023-08-03 10:05 ` Conor Dooley 2023-08-03 10:05 ` Conor Dooley 2023-08-04 7:48 ` Dylan Jhong 2023-08-04 7:48 ` Dylan Jhong 2023-08-08 11:23 ` Alexandre Ghiti 2023-08-08 11:23 ` Alexandre Ghiti 2023-08-08 23:55 ` Guo Ren 2023-08-08 23:55 ` Guo Ren 2023-08-10 16:00 ` Palmer Dabbelt 2023-08-10 16:00 ` Palmer Dabbelt 2023-08-10 16:22 ` Dylan Jhong 2023-08-10 16:22 ` Dylan Jhong 2023-08-10 19:39 ` Palmer Dabbelt 2023-08-10 19:39 ` Palmer Dabbelt 2023-08-08 23:47 ` Guo Ren 2023-08-08 23:47 ` Guo Ren 2023-08-10 19:50 ` patchwork-bot+linux-riscv 2023-08-10 19:50 ` patchwork-bot+linux-riscv
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