From: Charlie Jenkins <charlie@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: charlie@rivosinc.com, conor@kernel.org, paul.walmsley@sifive.com, palmer@rivosinc.com, aou@eecs.berkeley.edu, anup@brainfault.org, konstantin@linuxfoundation.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-mm@kvack.org, mick@ics.forth.gr, jrtc27@jrtc27.com, rdunlap@infradead.org, alexghiti@rivosinc.com Subject: [PATCH v8 3/4] RISC-V: mm: Update pgtable comment documentation Date: Thu, 27 Jul 2023 14:26:28 -0700 [thread overview] Message-ID: <20230727212647.4182407-4-charlie@rivosinc.com> (raw) In-Reply-To: <20230727212647.4182407-1-charlie@rivosinc.com> sv57 is supported in the kernel so pgtable.h should reflect that. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> --- arch/riscv/include/asm/pgtable.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index c76a1ef094a4..b551467a1dd8 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -848,14 +848,16 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte) * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. * Note that PGDIR_SIZE must evenly divide TASK_SIZE. * Task size is: - * - 0x9fc00000 (~2.5GB) for RV32. - * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu - * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu + * - 0x9fc00000 (~2.5GB) for RV32. + * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu + * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu + * - 0x100000000000000 ( 64PB) for RV64 using SV57 mmu * * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V * Instruction Set Manual Volume II: Privileged Architecture" states that * "load and store effective addresses, which are 64bits, must have bits * 63–48 all equal to bit 47, or else a page-fault exception will occur." + * Similarly for SV57, bits 63–57 must be equal to bit 56. */ #ifdef CONFIG_64BIT #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) -- 2.41.0
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From: Charlie Jenkins <charlie@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: charlie@rivosinc.com, conor@kernel.org, paul.walmsley@sifive.com, palmer@rivosinc.com, aou@eecs.berkeley.edu, anup@brainfault.org, konstantin@linuxfoundation.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-mm@kvack.org, mick@ics.forth.gr, jrtc27@jrtc27.com, rdunlap@infradead.org, alexghiti@rivosinc.com Subject: [PATCH v8 3/4] RISC-V: mm: Update pgtable comment documentation Date: Thu, 27 Jul 2023 14:26:28 -0700 [thread overview] Message-ID: <20230727212647.4182407-4-charlie@rivosinc.com> (raw) In-Reply-To: <20230727212647.4182407-1-charlie@rivosinc.com> sv57 is supported in the kernel so pgtable.h should reflect that. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> --- arch/riscv/include/asm/pgtable.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index c76a1ef094a4..b551467a1dd8 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -848,14 +848,16 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte) * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. * Note that PGDIR_SIZE must evenly divide TASK_SIZE. * Task size is: - * - 0x9fc00000 (~2.5GB) for RV32. - * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu - * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu + * - 0x9fc00000 (~2.5GB) for RV32. + * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu + * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu + * - 0x100000000000000 ( 64PB) for RV64 using SV57 mmu * * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V * Instruction Set Manual Volume II: Privileged Architecture" states that * "load and store effective addresses, which are 64bits, must have bits * 63–48 all equal to bit 47, or else a page-fault exception will occur." + * Similarly for SV57, bits 63–57 must be equal to bit 56. */ #ifdef CONFIG_64BIT #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) -- 2.41.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-07-27 21:27 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-07-27 21:26 [PATCH v8 0/4] RISC-V: mm: Make SV48 the default address space Charlie Jenkins 2023-07-27 21:26 ` Charlie Jenkins 2023-07-27 21:26 ` [PATCH v8 1/4] RISC-V: mm: Restrict address space for sv39,sv48,sv57 Charlie Jenkins 2023-07-27 21:26 ` Charlie Jenkins 2023-08-06 9:53 ` Alexandre Ghiti 2023-08-06 9:53 ` Alexandre Ghiti 2023-08-07 21:12 ` Charlie Jenkins 2023-08-07 21:12 ` Charlie Jenkins 2023-07-27 21:26 ` [PATCH v8 2/4] RISC-V: mm: Add tests for RISC-V mm Charlie Jenkins 2023-07-27 21:26 ` Charlie Jenkins 2023-08-06 10:06 ` Alexandre Ghiti 2023-08-06 10:06 ` Alexandre Ghiti 2023-08-07 17:53 ` Charlie Jenkins 2023-08-07 17:53 ` Charlie Jenkins 2023-07-27 21:26 ` Charlie Jenkins [this message] 2023-07-27 21:26 ` [PATCH v8 3/4] RISC-V: mm: Update pgtable comment documentation Charlie Jenkins 2023-07-27 21:26 ` [PATCH v8 4/4] RISC-V: mm: Document mmap changes Charlie Jenkins 2023-07-27 21:26 ` Charlie Jenkins 2023-08-06 10:08 ` Alexandre Ghiti 2023-08-06 10:08 ` Alexandre Ghiti
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