From: Miquel Raynal <miquel.raynal@bootlin.com> To: Lizhi Hou <lizhi.hou@amd.com>, Brian Xu <brian.xu@amd.com>, Raj Kumar Rampelli <raj.kumar.rampelli@amd.com>, Vinod Koul <vkoul@kernel.org> Cc: Michal Simek <michal.simek@amd.com>, Max Zhen <max.zhen@amd.com>, Sonal Santan <sonal.santan@amd.com>, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Miquel Raynal <miquel.raynal@bootlin.com>, stable@vger.kernel.org Subject: [PATCH 1/4] dmaengine: xilinx: xdma: Fix interrupt vector setting Date: Mon, 31 Jul 2023 12:14:39 +0200 [thread overview] Message-ID: <20230731101442.792514-2-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20230731101442.792514-1-miquel.raynal@bootlin.com> A couple of hardware registers need to be set to reflect which interrupts have been allocated to the device. Each register is 32-bit wide and can receive four 8-bit values. If we provide any other interrupt number than four, the irq_num variable will never be 0 within the while check and the while block will loop forever. There is an easy way to prevent this: just break the for loop when we reach "irq_num == 0", which anyway means all interrupts have been processed. Cc: stable@vger.kernel.org Fixes: 17ce252266c7 ("dmaengine: xilinx: xdma: Add xilinx xdma driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/dma/xilinx/xdma.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 93ee298d52b8..359123526dd0 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -668,6 +668,8 @@ static int xdma_set_vector_reg(struct xdma_device *xdev, u32 vec_tbl_start, val |= irq_start << shift; irq_start++; irq_num--; + if (!irq_num) + break; } /* write IRQ register */ -- 2.34.1
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From: Miquel Raynal <miquel.raynal@bootlin.com> To: Lizhi Hou <lizhi.hou@amd.com>, Brian Xu <brian.xu@amd.com>, Raj Kumar Rampelli <raj.kumar.rampelli@amd.com>, Vinod Koul <vkoul@kernel.org> Cc: Michal Simek <michal.simek@amd.com>, Max Zhen <max.zhen@amd.com>, Sonal Santan <sonal.santan@amd.com>, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Miquel Raynal <miquel.raynal@bootlin.com>, stable@vger.kernel.org Subject: [PATCH 1/4] dmaengine: xilinx: xdma: Fix interrupt vector setting Date: Mon, 31 Jul 2023 12:14:39 +0200 [thread overview] Message-ID: <20230731101442.792514-2-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20230731101442.792514-1-miquel.raynal@bootlin.com> A couple of hardware registers need to be set to reflect which interrupts have been allocated to the device. Each register is 32-bit wide and can receive four 8-bit values. If we provide any other interrupt number than four, the irq_num variable will never be 0 within the while check and the while block will loop forever. There is an easy way to prevent this: just break the for loop when we reach "irq_num == 0", which anyway means all interrupts have been processed. Cc: stable@vger.kernel.org Fixes: 17ce252266c7 ("dmaengine: xilinx: xdma: Add xilinx xdma driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/dma/xilinx/xdma.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 93ee298d52b8..359123526dd0 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -668,6 +668,8 @@ static int xdma_set_vector_reg(struct xdma_device *xdev, u32 vec_tbl_start, val |= irq_start << shift; irq_start++; irq_num--; + if (!irq_num) + break; } /* write IRQ register */ -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-07-31 10:14 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-07-31 10:14 [PATCH 0/4] dmaengine: xdma: Cyclic transfers support Miquel Raynal 2023-07-31 10:14 ` Miquel Raynal 2023-07-31 10:14 ` Miquel Raynal [this message] 2023-07-31 10:14 ` [PATCH 1/4] dmaengine: xilinx: xdma: Fix interrupt vector setting Miquel Raynal 2023-07-31 23:33 ` Lizhi Hou 2023-07-31 23:33 ` Lizhi Hou 2023-07-31 10:14 ` [PATCH 2/4] dmaengine: xilinx: xdma: Fix typo Miquel Raynal 2023-07-31 10:14 ` Miquel Raynal 2023-07-31 10:14 ` [PATCH 3/4] dmaengine: xilinx: xdma: Prepare the introduction of cyclic transfers Miquel Raynal 2023-07-31 10:14 ` Miquel Raynal 2023-07-31 10:14 ` [PATCH 4/4] dmaengine: xilinx: xdma: Support " Miquel Raynal 2023-07-31 10:14 ` Miquel Raynal 2023-07-31 14:39 ` kernel test robot 2023-07-31 14:39 ` kernel test robot 2023-07-31 23:53 ` Lizhi Hou 2023-07-31 23:53 ` Lizhi Hou 2023-08-01 7:20 ` Miquel Raynal 2023-08-01 7:20 ` Miquel Raynal 2023-08-01 18:44 ` (subset) [PATCH 0/4] dmaengine: xdma: Cyclic transfers support Vinod Koul 2023-08-01 18:44 ` Vinod Koul 2023-08-01 18:59 ` Miquel Raynal 2023-08-01 18:59 ` Miquel Raynal
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