From: Chen-Yu Tsai <wenst@chromium.org>
To: Lee Jones <lee@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Mark Brown <broonie@kernel.org>
Cc: Chen-Yu Tsai <wenst@chromium.org>,
Zhiyong Tao <zhiyong.tao@mediatek.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: [PATCH 8/9] regulator: mt6358: Add supply names for MT6366 regulators
Date: Thu, 3 Aug 2023 15:42:46 +0800 [thread overview]
Message-ID: <20230803074249.3065586-9-wenst@chromium.org> (raw)
In-Reply-To: <20230803074249.3065586-1-wenst@chromium.org>
The DT bindings for MT6366 regulator defines the supply names for the
PMIC.
Add support for them by adding .supply_name field settings for each
regulator. The buck regulators each have their own supply whose name
can be derived from the regulator name. The LDOs have shared supplies.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
drivers/regulator/mt6358-regulator.c | 73 ++++++++++++++--------------
1 file changed, 36 insertions(+), 37 deletions(-)
diff --git a/drivers/regulator/mt6358-regulator.c b/drivers/regulator/mt6358-regulator.c
index c9fd5904d13f..b3de933c58b3 100644
--- a/drivers/regulator/mt6358-regulator.c
+++ b/drivers/regulator/mt6358-regulator.c
@@ -139,6 +139,7 @@ struct mt6358_regulator_info {
[MT6366_ID_##vreg] = { \
.desc = { \
.name = #vreg, \
+ .supply_name = "vsys_" match, \
.of_match = of_match_ptr(match), \
.ops = &mt6358_volt_range_ops, \
.type = REGULATOR_VOLTAGE, \
@@ -161,10 +162,11 @@ struct mt6358_regulator_info {
.modeset_mask = BIT(_modeset_shift), \
}
-#define MT6366_LDO(match, vreg, volt_ranges, enreg, enbit, vosel, vosel_mask) \
+#define MT6366_LDO(match, vreg, volt_ranges, supply, enreg, enbit, vosel, vosel_mask) \
[MT6366_ID_##vreg] = { \
.desc = { \
.name = #vreg, \
+ .supply_name = supply, \
.of_match = of_match_ptr(match), \
.ops = &mt6358_volt_table_ops, \
.type = REGULATOR_VOLTAGE, \
@@ -185,12 +187,13 @@ struct mt6358_regulator_info {
.qi = BIT(15), \
}
-#define MT6366_LDO1(match, vreg, min, max, step, \
+#define MT6366_LDO1(match, vreg, supply, min, max, step, \
_da_vsel_reg, _da_vsel_mask, \
vosel, vosel_mask) \
[MT6366_ID_##vreg] = { \
.desc = { \
.name = #vreg, \
+ .supply_name = supply, \
.of_match = of_match_ptr(match), \
.ops = &mt6358_volt_range_ops, \
.type = REGULATOR_VOLTAGE, \
@@ -210,11 +213,12 @@ struct mt6358_regulator_info {
.qi = BIT(0), \
}
-#define MT6366_REG_FIXED(match, vreg, \
+#define MT6366_REG_FIXED(match, vreg, supply, \
enreg, enbit, volt) \
[MT6366_ID_##vreg] = { \
.desc = { \
.name = #vreg, \
+ .supply_name = supply, \
.of_match = of_match_ptr(match), \
.ops = &mt6358_volt_fixed_ops, \
.type = REGULATOR_VOLTAGE, \
@@ -589,57 +593,52 @@ static const struct mt6358_regulator_info mt6366_regulators[] = {
0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, MT6358_VMODEM_ANA_CON0, 8),
MT6366_BUCK("vs1", VS1, 1000000, 2587500, 12500,
0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, MT6358_VS1_ANA_CON0, 8),
- MT6366_REG_FIXED("vrf12", VRF12,
- MT6358_LDO_VRF12_CON0, 0, 1200000),
- MT6366_REG_FIXED("vio18", VIO18,
- MT6358_LDO_VIO18_CON0, 0, 1800000),
- MT6366_REG_FIXED("vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
- MT6366_REG_FIXED("vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
- MT6366_REG_FIXED("vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
- MT6366_REG_FIXED("vaux18", VAUX18,
- MT6358_LDO_VAUX18_CON0, 0, 1800000),
- MT6366_REG_FIXED("vbif28", VBIF28,
- MT6358_LDO_VBIF28_CON0, 0, 2800000),
- MT6366_REG_FIXED("vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
- MT6366_REG_FIXED("va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
- MT6366_REG_FIXED("vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
- MT6366_REG_FIXED("vaud28", VAUD28,
- MT6358_LDO_VAUD28_CON0, 0, 2800000),
- MT6366_LDO("vdram2", VDRAM2, vdram2,
+ MT6366_REG_FIXED("vrf12", VRF12, "vs2_ldo2", MT6358_LDO_VRF12_CON0, 0, 1200000),
+ MT6366_REG_FIXED("vio18", VIO18, "vs1_ldo1", MT6358_LDO_VIO18_CON0, 0, 1800000),
+ MT6366_REG_FIXED("vfe28", VFE28, "vsys_ldo1", MT6358_LDO_VFE28_CON0, 0, 2800000),
+ MT6366_REG_FIXED("vcn28", VCN28, "vsys_ldo1", MT6358_LDO_VCN28_CON0, 0, 2800000),
+ MT6366_REG_FIXED("vxo22", VXO22, "vsys_ldo1", MT6358_LDO_VXO22_CON0, 0, 2200000),
+ MT6366_REG_FIXED("vaux18", VAUX18, "vsys_ldo1", MT6358_LDO_VAUX18_CON0, 0, 1800000),
+ MT6366_REG_FIXED("vbif28", VBIF28, "vsys_ldo1", MT6358_LDO_VBIF28_CON0, 0, 2800000),
+ MT6366_REG_FIXED("vio28", VIO28, "vsys_ldo2", MT6358_LDO_VIO28_CON0, 0, 2800000),
+ MT6366_REG_FIXED("va12", VA12, "vs2_ldo2", MT6358_LDO_VA12_CON0, 0, 1200000),
+ MT6366_REG_FIXED("vrf18", VRF18, "vs1_ldo1", MT6358_LDO_VRF18_CON0, 0, 1800000),
+ MT6366_REG_FIXED("vaud28", VAUD28, "vsys_ldo1", MT6358_LDO_VAUD28_CON0, 0, 2800000),
+ MT6366_LDO("vdram2", VDRAM2, vdram2, "vs2_ldo1",
MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10),
- MT6366_LDO("vsim1", VSIM1, vsim,
+ MT6366_LDO("vsim1", VSIM1, vsim, "vsys_ldo1",
MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
- MT6366_LDO("vibr", VIBR, vibr,
+ MT6366_LDO("vibr", VIBR, vibr, "vsys_ldo3",
MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
- MT6366_LDO("vusb", VUSB, vusb,
+ MT6366_LDO("vusb", VUSB, vusb, "vsys_ldo1",
MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
- MT6366_LDO("vefuse", VEFUSE, vefuse,
+ MT6366_LDO("vefuse", VEFUSE, vefuse, "vs1_ldo1",
MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
- MT6366_LDO("vmch", VMCH, vmch_vemc,
+ MT6366_LDO("vmch", VMCH, vmch_vemc, "vsys_ldo2",
MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
- MT6366_LDO("vemc", VEMC, vmch_vemc,
+ MT6366_LDO("vemc", VEMC, vmch_vemc, "vsys_ldo3",
MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
- MT6366_LDO("vcn33", VCN33, vcn33,
+ MT6366_LDO("vcn33", VCN33, vcn33, "vsys_ldo3",
MT6358_LDO_VCN33_CON0_0, 0, MT6358_VCN33_ANA_CON0, 0x300),
- MT6366_LDO("vmc", VMC, vmc,
+ MT6366_LDO("vmc", VMC, vmc, "vsys_ldo2",
MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
- MT6366_LDO("vsim2", VSIM2, vsim,
+ MT6366_LDO("vsim2", VSIM2, vsim, "vsys_ldo2",
MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
- MT6366_LDO("vcn18", VCN18, mt6366_vcn18_vm18,
+ MT6366_LDO("vcn18", VCN18, mt6366_vcn18_vm18, "vs1_ldo1",
MT6358_LDO_VCN18_CON0, 0, MT6358_VCN18_ANA_CON0, 0xf00),
- MT6366_LDO("vm18", VM18, mt6366_vcn18_vm18,
+ MT6366_LDO("vm18", VM18, mt6366_vcn18_vm18, "vs1_ldo1",
MT6358_LDO_VM18_CON0, 0, MT6358_VM18_ANA_CON0, 0xf00),
- MT6366_LDO("vmddr", VMDDR, mt6366_vmddr,
+ MT6366_LDO("vmddr", VMDDR, mt6366_vmddr, "vs2_ldo1",
MT6358_LDO_VMDDR_CON0, 0, MT6358_VMDDR_ANA_CON0, 0xf00),
- MT6366_LDO1("vsram-proc11", VSRAM_PROC11, 500000, 1293750, 6250,
+ MT6366_LDO1("vsram-proc11", VSRAM_PROC11, "vs2_ldo3", 500000, 1293750, 6250,
MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON0, 0x7f),
- MT6366_LDO1("vsram-others", VSRAM_OTHERS, 500000, 1293750, 6250,
+ MT6366_LDO1("vsram-others", VSRAM_OTHERS, "vs2_ldo3", 500000, 1293750, 6250,
MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON2, 0x7f),
- MT6366_LDO1("vsram-gpu", VSRAM_GPU, 500000, 1293750, 6250,
+ MT6366_LDO1("vsram-gpu", VSRAM_GPU, "vs2_ldo3", 500000, 1293750, 6250,
MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON3, 0x7f),
- MT6366_LDO1("vsram-proc12", VSRAM_PROC12, 500000, 1293750, 6250,
+ MT6366_LDO1("vsram-proc12", VSRAM_PROC12, "vs2_ldo3", 500000, 1293750, 6250,
MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON1, 0x7f),
- MT6366_LDO1("vsram-core", VSRAM_CORE, 500000, 1293750, 6250,
+ MT6366_LDO1("vsram-core", VSRAM_CORE, "vs2_ldo3", 500000, 1293750, 6250,
MT6358_LDO_VSRAM_CORE_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON5, 0x7f),
};
--
2.41.0.585.gd2178a4bd4-goog
WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wenst@chromium.org>
To: Lee Jones <lee@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Mark Brown <broonie@kernel.org>
Cc: Chen-Yu Tsai <wenst@chromium.org>,
Zhiyong Tao <zhiyong.tao@mediatek.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: [PATCH 8/9] regulator: mt6358: Add supply names for MT6366 regulators
Date: Thu, 3 Aug 2023 15:42:46 +0800 [thread overview]
Message-ID: <20230803074249.3065586-9-wenst@chromium.org> (raw)
In-Reply-To: <20230803074249.3065586-1-wenst@chromium.org>
The DT bindings for MT6366 regulator defines the supply names for the
PMIC.
Add support for them by adding .supply_name field settings for each
regulator. The buck regulators each have their own supply whose name
can be derived from the regulator name. The LDOs have shared supplies.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
drivers/regulator/mt6358-regulator.c | 73 ++++++++++++++--------------
1 file changed, 36 insertions(+), 37 deletions(-)
diff --git a/drivers/regulator/mt6358-regulator.c b/drivers/regulator/mt6358-regulator.c
index c9fd5904d13f..b3de933c58b3 100644
--- a/drivers/regulator/mt6358-regulator.c
+++ b/drivers/regulator/mt6358-regulator.c
@@ -139,6 +139,7 @@ struct mt6358_regulator_info {
[MT6366_ID_##vreg] = { \
.desc = { \
.name = #vreg, \
+ .supply_name = "vsys_" match, \
.of_match = of_match_ptr(match), \
.ops = &mt6358_volt_range_ops, \
.type = REGULATOR_VOLTAGE, \
@@ -161,10 +162,11 @@ struct mt6358_regulator_info {
.modeset_mask = BIT(_modeset_shift), \
}
-#define MT6366_LDO(match, vreg, volt_ranges, enreg, enbit, vosel, vosel_mask) \
+#define MT6366_LDO(match, vreg, volt_ranges, supply, enreg, enbit, vosel, vosel_mask) \
[MT6366_ID_##vreg] = { \
.desc = { \
.name = #vreg, \
+ .supply_name = supply, \
.of_match = of_match_ptr(match), \
.ops = &mt6358_volt_table_ops, \
.type = REGULATOR_VOLTAGE, \
@@ -185,12 +187,13 @@ struct mt6358_regulator_info {
.qi = BIT(15), \
}
-#define MT6366_LDO1(match, vreg, min, max, step, \
+#define MT6366_LDO1(match, vreg, supply, min, max, step, \
_da_vsel_reg, _da_vsel_mask, \
vosel, vosel_mask) \
[MT6366_ID_##vreg] = { \
.desc = { \
.name = #vreg, \
+ .supply_name = supply, \
.of_match = of_match_ptr(match), \
.ops = &mt6358_volt_range_ops, \
.type = REGULATOR_VOLTAGE, \
@@ -210,11 +213,12 @@ struct mt6358_regulator_info {
.qi = BIT(0), \
}
-#define MT6366_REG_FIXED(match, vreg, \
+#define MT6366_REG_FIXED(match, vreg, supply, \
enreg, enbit, volt) \
[MT6366_ID_##vreg] = { \
.desc = { \
.name = #vreg, \
+ .supply_name = supply, \
.of_match = of_match_ptr(match), \
.ops = &mt6358_volt_fixed_ops, \
.type = REGULATOR_VOLTAGE, \
@@ -589,57 +593,52 @@ static const struct mt6358_regulator_info mt6366_regulators[] = {
0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, MT6358_VMODEM_ANA_CON0, 8),
MT6366_BUCK("vs1", VS1, 1000000, 2587500, 12500,
0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, MT6358_VS1_ANA_CON0, 8),
- MT6366_REG_FIXED("vrf12", VRF12,
- MT6358_LDO_VRF12_CON0, 0, 1200000),
- MT6366_REG_FIXED("vio18", VIO18,
- MT6358_LDO_VIO18_CON0, 0, 1800000),
- MT6366_REG_FIXED("vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
- MT6366_REG_FIXED("vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
- MT6366_REG_FIXED("vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
- MT6366_REG_FIXED("vaux18", VAUX18,
- MT6358_LDO_VAUX18_CON0, 0, 1800000),
- MT6366_REG_FIXED("vbif28", VBIF28,
- MT6358_LDO_VBIF28_CON0, 0, 2800000),
- MT6366_REG_FIXED("vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
- MT6366_REG_FIXED("va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
- MT6366_REG_FIXED("vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
- MT6366_REG_FIXED("vaud28", VAUD28,
- MT6358_LDO_VAUD28_CON0, 0, 2800000),
- MT6366_LDO("vdram2", VDRAM2, vdram2,
+ MT6366_REG_FIXED("vrf12", VRF12, "vs2_ldo2", MT6358_LDO_VRF12_CON0, 0, 1200000),
+ MT6366_REG_FIXED("vio18", VIO18, "vs1_ldo1", MT6358_LDO_VIO18_CON0, 0, 1800000),
+ MT6366_REG_FIXED("vfe28", VFE28, "vsys_ldo1", MT6358_LDO_VFE28_CON0, 0, 2800000),
+ MT6366_REG_FIXED("vcn28", VCN28, "vsys_ldo1", MT6358_LDO_VCN28_CON0, 0, 2800000),
+ MT6366_REG_FIXED("vxo22", VXO22, "vsys_ldo1", MT6358_LDO_VXO22_CON0, 0, 2200000),
+ MT6366_REG_FIXED("vaux18", VAUX18, "vsys_ldo1", MT6358_LDO_VAUX18_CON0, 0, 1800000),
+ MT6366_REG_FIXED("vbif28", VBIF28, "vsys_ldo1", MT6358_LDO_VBIF28_CON0, 0, 2800000),
+ MT6366_REG_FIXED("vio28", VIO28, "vsys_ldo2", MT6358_LDO_VIO28_CON0, 0, 2800000),
+ MT6366_REG_FIXED("va12", VA12, "vs2_ldo2", MT6358_LDO_VA12_CON0, 0, 1200000),
+ MT6366_REG_FIXED("vrf18", VRF18, "vs1_ldo1", MT6358_LDO_VRF18_CON0, 0, 1800000),
+ MT6366_REG_FIXED("vaud28", VAUD28, "vsys_ldo1", MT6358_LDO_VAUD28_CON0, 0, 2800000),
+ MT6366_LDO("vdram2", VDRAM2, vdram2, "vs2_ldo1",
MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10),
- MT6366_LDO("vsim1", VSIM1, vsim,
+ MT6366_LDO("vsim1", VSIM1, vsim, "vsys_ldo1",
MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
- MT6366_LDO("vibr", VIBR, vibr,
+ MT6366_LDO("vibr", VIBR, vibr, "vsys_ldo3",
MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
- MT6366_LDO("vusb", VUSB, vusb,
+ MT6366_LDO("vusb", VUSB, vusb, "vsys_ldo1",
MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
- MT6366_LDO("vefuse", VEFUSE, vefuse,
+ MT6366_LDO("vefuse", VEFUSE, vefuse, "vs1_ldo1",
MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
- MT6366_LDO("vmch", VMCH, vmch_vemc,
+ MT6366_LDO("vmch", VMCH, vmch_vemc, "vsys_ldo2",
MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
- MT6366_LDO("vemc", VEMC, vmch_vemc,
+ MT6366_LDO("vemc", VEMC, vmch_vemc, "vsys_ldo3",
MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
- MT6366_LDO("vcn33", VCN33, vcn33,
+ MT6366_LDO("vcn33", VCN33, vcn33, "vsys_ldo3",
MT6358_LDO_VCN33_CON0_0, 0, MT6358_VCN33_ANA_CON0, 0x300),
- MT6366_LDO("vmc", VMC, vmc,
+ MT6366_LDO("vmc", VMC, vmc, "vsys_ldo2",
MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
- MT6366_LDO("vsim2", VSIM2, vsim,
+ MT6366_LDO("vsim2", VSIM2, vsim, "vsys_ldo2",
MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
- MT6366_LDO("vcn18", VCN18, mt6366_vcn18_vm18,
+ MT6366_LDO("vcn18", VCN18, mt6366_vcn18_vm18, "vs1_ldo1",
MT6358_LDO_VCN18_CON0, 0, MT6358_VCN18_ANA_CON0, 0xf00),
- MT6366_LDO("vm18", VM18, mt6366_vcn18_vm18,
+ MT6366_LDO("vm18", VM18, mt6366_vcn18_vm18, "vs1_ldo1",
MT6358_LDO_VM18_CON0, 0, MT6358_VM18_ANA_CON0, 0xf00),
- MT6366_LDO("vmddr", VMDDR, mt6366_vmddr,
+ MT6366_LDO("vmddr", VMDDR, mt6366_vmddr, "vs2_ldo1",
MT6358_LDO_VMDDR_CON0, 0, MT6358_VMDDR_ANA_CON0, 0xf00),
- MT6366_LDO1("vsram-proc11", VSRAM_PROC11, 500000, 1293750, 6250,
+ MT6366_LDO1("vsram-proc11", VSRAM_PROC11, "vs2_ldo3", 500000, 1293750, 6250,
MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON0, 0x7f),
- MT6366_LDO1("vsram-others", VSRAM_OTHERS, 500000, 1293750, 6250,
+ MT6366_LDO1("vsram-others", VSRAM_OTHERS, "vs2_ldo3", 500000, 1293750, 6250,
MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON2, 0x7f),
- MT6366_LDO1("vsram-gpu", VSRAM_GPU, 500000, 1293750, 6250,
+ MT6366_LDO1("vsram-gpu", VSRAM_GPU, "vs2_ldo3", 500000, 1293750, 6250,
MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON3, 0x7f),
- MT6366_LDO1("vsram-proc12", VSRAM_PROC12, 500000, 1293750, 6250,
+ MT6366_LDO1("vsram-proc12", VSRAM_PROC12, "vs2_ldo3", 500000, 1293750, 6250,
MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON1, 0x7f),
- MT6366_LDO1("vsram-core", VSRAM_CORE, 500000, 1293750, 6250,
+ MT6366_LDO1("vsram-core", VSRAM_CORE, "vs2_ldo3", 500000, 1293750, 6250,
MT6358_LDO_VSRAM_CORE_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON5, 0x7f),
};
--
2.41.0.585.gd2178a4bd4-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-08-03 7:55 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-03 7:42 [PATCH 0/9] regulator: mt6366: Split out of MT6358 and cleanup Chen-Yu Tsai
2023-08-03 7:42 ` Chen-Yu Tsai
2023-08-03 7:42 ` [PATCH 1/9] dt-bindings: mfd: mt6397: Split out compatible for MediaTek MT6366 PMIC Chen-Yu Tsai
2023-08-03 7:42 ` Chen-Yu Tsai
2023-08-04 15:31 ` Conor Dooley
2023-08-04 15:31 ` Conor Dooley
2023-08-03 7:42 ` [PATCH 2/9] mfd: mt6358: Add registers for MT6366 specific regulators Chen-Yu Tsai
2023-08-03 7:42 ` Chen-Yu Tsai
2023-08-03 7:42 ` [PATCH 3/9] mfd: mt6397: Split MediaTek MT6366 PMIC out of MT6358 Chen-Yu Tsai
2023-08-03 7:42 ` Chen-Yu Tsai
2023-08-03 9:01 ` AngeloGioacchino Del Regno
2023-08-03 9:01 ` AngeloGioacchino Del Regno
2023-08-04 3:47 ` Chen-Yu Tsai
2023-08-04 3:47 ` Chen-Yu Tsai
2023-08-04 6:39 ` AngeloGioacchino Del Regno
2023-08-04 6:39 ` AngeloGioacchino Del Regno
2023-08-03 7:42 ` [PATCH 4/9] regulator: dt-bindings: mediatek: Add MT6366 PMIC Chen-Yu Tsai
2023-08-03 7:42 ` Chen-Yu Tsai
2023-08-07 6:23 ` Krzysztof Kozlowski
2023-08-07 6:23 ` Krzysztof Kozlowski
2023-08-07 6:30 ` Chen-Yu Tsai
2023-08-07 6:30 ` Chen-Yu Tsai
2023-08-07 6:36 ` Krzysztof Kozlowski
2023-08-07 6:36 ` Krzysztof Kozlowski
2023-08-03 7:42 ` [PATCH 5/9] regulator: mt6358: fix and drop type prefix in MT6366 regulator node names Chen-Yu Tsai
2023-08-03 7:42 ` Chen-Yu Tsai
2023-08-03 9:01 ` AngeloGioacchino Del Regno
2023-08-03 9:01 ` AngeloGioacchino Del Regno
2023-08-04 10:13 ` Eugen Hristev
2023-08-04 10:13 ` Eugen Hristev
2023-08-07 3:54 ` Chen-Yu Tsai
2023-08-07 3:54 ` Chen-Yu Tsai
2023-08-03 7:42 ` [PATCH 6/9] regulator: mt6358: Make MT6366 vcn18 LDO configurable Chen-Yu Tsai
2023-08-03 7:42 ` Chen-Yu Tsai
2023-08-03 9:01 ` AngeloGioacchino Del Regno
2023-08-03 9:01 ` AngeloGioacchino Del Regno
2023-08-03 7:42 ` [PATCH 7/9] regulator: mt6358: Add missing regulators for MT6366 Chen-Yu Tsai
2023-08-03 7:42 ` Chen-Yu Tsai
2023-08-03 9:01 ` AngeloGioacchino Del Regno
2023-08-03 9:01 ` AngeloGioacchino Del Regno
2023-08-03 7:42 ` Chen-Yu Tsai [this message]
2023-08-03 7:42 ` [PATCH 8/9] regulator: mt6358: Add supply names for MT6366 regulators Chen-Yu Tsai
2023-08-03 9:01 ` AngeloGioacchino Del Regno
2023-08-03 9:01 ` AngeloGioacchino Del Regno
2023-08-03 7:42 ` [PATCH 9/9] soc: mediatek: pwrap: add support for MT6366 PMIC Chen-Yu Tsai
2023-08-03 7:42 ` Chen-Yu Tsai
2023-08-03 9:01 ` AngeloGioacchino Del Regno
2023-08-03 9:01 ` AngeloGioacchino Del Regno
2023-08-04 3:49 ` Chen-Yu Tsai
2023-08-04 3:49 ` Chen-Yu Tsai
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230803074249.3065586-9-wenst@chromium.org \
--to=wenst@chromium.org \
--cc=angelogioacchino.delregno@collabora.com \
--cc=broonie@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=lee@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=robh+dt@kernel.org \
--cc=zhiyong.tao@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.