[v1, 0/3] riscv: fix ptrace and export VLENB

[Andy Chiu <andy.chiu@sifive.com>]

We add a vlenb field in Vector context and save it with the
riscv_vstate_save() macro. It should not cause performance regression as
VLENB is a design-time constant and is frequently used by hardware.
Also, adding this field into the __sc_riscv_v_state may benifit us on a
future compatibility issue becuse a hardware may have writable VLENB.

Adding and saving VLENB have an immediate benifit as it gives ptrace a
better view of the Vector extension and makes it possible to reconstruct
Vector register files from the dump without doing an additional csr read.

This patchset also sync the number of note types between us and gdb for
riscv to solve a conflicting note.

This is not an ABI break given that 6.5 has not been released yet.

The series is tested on a virt QEMU by verifying VLENB is saved in
ptrace, coredump, and signal stack.

[1] https://sourceware.org/pipermail/gdb-patches/2023-August/201492.html

Andy Chiu (2):
  RISC-V: vector: export VLENB csr in __sc_riscv_v_state
  RISC-V: Add ptrace support for vectors

Palmer Dabbelt (1):
  RISC-V: Remove ptrace support for vectors

 arch/riscv/include/asm/vector.h      | 3 ++-
 arch/riscv/include/uapi/asm/ptrace.h | 1 +
 include/uapi/linux/elf.h             | 3 ++-
 3 files changed, 5 insertions(+), 2 deletions(-)

-- 
2.17.1


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