From: Prabhakar <prabhakar.csengg@gmail.com>
To: Arnd Bergmann <arnd@arndb.de>,
Conor Dooley <conor.dooley@microchip.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Guo Ren <guoren@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Samuel Holland <samuel@sholland.org>,
linux-riscv@lists.infradead.org,
Christoph Hellwig <hch@infradead.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v12 1/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list
Date: Fri, 18 Aug 2023 14:57:18 +0100 [thread overview]
Message-ID: <20230818135723.80612-2-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20230818135723.80612-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add Andes Technology to the vendors list.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
---
v11 -> v12
* No change
v10 -> v11
* No change
v9 -> v10
* Included TB tag from Conor
v8 -> v9
* Included RB tag from Geert
v7 -> v8
* No change
v6 -> v7
* No change
v5 -> v6
* No change
v4 -> v5
* Included RB tags
RFC v3 -> v4
* New patch
---
arch/riscv/include/asm/vendorid_list.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index cb89af3f0704..e55407ace0c3 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -5,6 +5,7 @@
#ifndef ASM_VENDOR_LIST_H
#define ASM_VENDOR_LIST_H
+#define ANDESTECH_VENDOR_ID 0x31e
#define SIFIVE_VENDOR_ID 0x489
#define THEAD_VENDOR_ID 0x5b7
--
2.34.1
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WARNING: multiple messages have this Message-ID (diff)
From: Prabhakar <prabhakar.csengg@gmail.com>
To: Arnd Bergmann <arnd@arndb.de>,
Conor Dooley <conor.dooley@microchip.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Guo Ren <guoren@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Samuel Holland <samuel@sholland.org>,
linux-riscv@lists.infradead.org,
Christoph Hellwig <hch@infradead.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v12 1/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list
Date: Fri, 18 Aug 2023 14:57:18 +0100 [thread overview]
Message-ID: <20230818135723.80612-2-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20230818135723.80612-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add Andes Technology to the vendors list.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
---
v11 -> v12
* No change
v10 -> v11
* No change
v9 -> v10
* Included TB tag from Conor
v8 -> v9
* Included RB tag from Geert
v7 -> v8
* No change
v6 -> v7
* No change
v5 -> v6
* No change
v4 -> v5
* Included RB tags
RFC v3 -> v4
* New patch
---
arch/riscv/include/asm/vendorid_list.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index cb89af3f0704..e55407ace0c3 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -5,6 +5,7 @@
#ifndef ASM_VENDOR_LIST_H
#define ASM_VENDOR_LIST_H
+#define ANDESTECH_VENDOR_ID 0x31e
#define SIFIVE_VENDOR_ID 0x489
#define THEAD_VENDOR_ID 0x5b7
--
2.34.1
next prev parent reply other threads:[~2023-08-18 13:57 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-18 13:57 [PATCH v12 0/6] Add non-coherent DMA support for AX45MP Prabhakar
2023-08-18 13:57 ` Prabhakar
2023-08-18 13:57 ` Prabhakar [this message]
2023-08-18 13:57 ` [PATCH v12 1/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2023-08-18 13:57 ` [PATCH v12 2/6] riscv: errata: Add Andes alternative ports Prabhakar
2023-08-18 13:57 ` Prabhakar
2023-08-18 13:57 ` [PATCH v12 3/6] riscv: mm: dma-noncoherent: nonstandard cache operations support Prabhakar
2023-08-18 13:57 ` Prabhakar
2023-08-24 12:36 ` Emil Renner Berthing
2023-08-24 12:36 ` Emil Renner Berthing
2023-08-18 13:57 ` [PATCH v12 4/6] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller Prabhakar
2023-08-18 13:57 ` Prabhakar
2023-08-18 13:57 ` [PATCH v12 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core Prabhakar
2023-08-18 13:57 ` Prabhakar
2023-08-18 13:57 ` [PATCH v12 6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Prabhakar
2023-08-18 13:57 ` Prabhakar
2023-08-30 20:30 ` [PATCH v12 0/6] Add non-coherent DMA support for AX45MP patchwork-bot+linux-riscv
2023-08-30 20:30 ` patchwork-bot+linux-riscv
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