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From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: [PATCH 6.1.y-cip 01/15] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels
Date: Mon, 21 Aug 2023 15:37:45 +0100	[thread overview]
Message-ID: <20230821143759.227105-2-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20230821143759.227105-1-biju.das.jz@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 38c042b59af0248a8b13f01b1a09d890997c9f6e upstream.

For half duplex channels we dont have separate interrupts for Tx and Rx
instead we have single interrupt Rt (where the signal for Rx and Tx is
muxed). To handle such a case install a handler in case we have a dma_rt
interrupt specified in the DT for the PIO mode.

Note, for backward compatibility we check if the Rx and Tx interrupts
are present first instead of checking Rt interrupt.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20230217185225.43310-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 sound/soc/sh/rz-ssi.c | 63 ++++++++++++++++++++++++++++++-------------
 1 file changed, 44 insertions(+), 19 deletions(-)

diff --git a/sound/soc/sh/rz-ssi.c b/sound/soc/sh/rz-ssi.c
index 5d6bae33ae34..d502aa55c5a8 100644
--- a/sound/soc/sh/rz-ssi.c
+++ b/sound/soc/sh/rz-ssi.c
@@ -109,6 +109,7 @@ struct rz_ssi_priv {
 	int irq_int;
 	int irq_tx;
 	int irq_rx;
+	int irq_rt;
 
 	spinlock_t lock;
 
@@ -565,6 +566,17 @@ static irqreturn_t rz_ssi_interrupt(int irq, void *data)
 		rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
 	}
 
+	if (irq == ssi->irq_rt) {
+		struct snd_pcm_substream *substream = strm->substream;
+
+		if (rz_ssi_stream_is_play(ssi, substream)) {
+			strm->transfer(ssi, &ssi->playback);
+		} else {
+			strm->transfer(ssi, &ssi->capture);
+			rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
+		}
+	}
+
 	return IRQ_HANDLED;
 }
 
@@ -993,26 +1005,39 @@ static int rz_ssi_probe(struct platform_device *pdev)
 	if (!rz_ssi_is_dma_enabled(ssi)) {
 		/* Tx and Rx interrupts (pio only) */
 		ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
-		if (ssi->irq_tx < 0)
-			return ssi->irq_tx;
-
-		ret = devm_request_irq(&pdev->dev, ssi->irq_tx,
-				       &rz_ssi_interrupt, 0,
-				       dev_name(&pdev->dev), ssi);
-		if (ret < 0)
-			return dev_err_probe(&pdev->dev, ret,
-					     "irq request error (dma_tx)\n");
-
 		ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
-		if (ssi->irq_rx < 0)
-			return ssi->irq_rx;
-
-		ret = devm_request_irq(&pdev->dev, ssi->irq_rx,
-				       &rz_ssi_interrupt, 0,
-				       dev_name(&pdev->dev), ssi);
-		if (ret < 0)
-			return dev_err_probe(&pdev->dev, ret,
-					     "irq request error (dma_rx)\n");
+		if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) {
+			ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt");
+			if (ssi->irq_rt < 0)
+				return ssi->irq_rt;
+
+			ret = devm_request_irq(&pdev->dev, ssi->irq_rt,
+					       &rz_ssi_interrupt, 0,
+					       dev_name(&pdev->dev), ssi);
+			if (ret < 0)
+				return dev_err_probe(&pdev->dev, ret,
+						"irq request error (dma_tx)\n");
+		} else {
+			if (ssi->irq_tx < 0)
+				return ssi->irq_tx;
+
+			if (ssi->irq_rx < 0)
+				return ssi->irq_rx;
+
+			ret = devm_request_irq(&pdev->dev, ssi->irq_tx,
+					       &rz_ssi_interrupt, 0,
+					       dev_name(&pdev->dev), ssi);
+			if (ret < 0)
+				return dev_err_probe(&pdev->dev, ret,
+						"irq request error (dma_tx)\n");
+
+			ret = devm_request_irq(&pdev->dev, ssi->irq_rx,
+					       &rz_ssi_interrupt, 0,
+					       dev_name(&pdev->dev), ssi);
+			if (ret < 0)
+				return dev_err_probe(&pdev->dev, ret,
+						"irq request error (dma_rx)\n");
+		}
 	}
 
 	ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
-- 
2.25.1



  reply	other threads:[~2023-08-21 14:38 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
2023-08-21 14:37 ` Biju Das [this message]
2023-08-21 14:37 ` [PATCH 6.1.y-cip 02/15] arm64: dts: renesas: rzg2ul-smarc: Move spi1 pinmux to carrier board DTSI Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 03/15] clk: renesas: r9a07g044: Drop WDT2 clock and reset entry Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 04/15] clk: renesas: r9a07g043: " Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 05/15] arm64: dts: renesas: rzg2l: Drop WDT2 nodes Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 06/15] arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodes Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 07/15] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 08/15] pinctrl: renesas: Add missing header(s) Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 09/15] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 10/15] arm64: dts: renesas: r9a07g043u: Add IRQC node Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 11/15] arm64: dts: renesas: r9a07g043u: Update pinctrl node to handle GPIO interrupts Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 12/15] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 13/15] arm64: dts: renesas: rzg2l: Add missing cache-level properties Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 14/15] arm64: dts: renesas: r9a07g043u: Add Cortex-A55 PMU node Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 15/15] arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems Biju Das
2023-08-22  8:44 ` [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Pavel Machek
2023-08-23  8:43   ` Pavel Machek

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