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From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>
Cc: Sergey Matyukevich <sergey.matyukevich@syntacore.com>,
	linux-riscv@lists.infradead.org, Heiko Stuebner <heiko@sntech.de>,
	linux-kernel@vger.kernel.org
Subject: [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding
Date: Sun, 27 Aug 2023 17:08:12 +0800	[thread overview]
Message-ID: <20230827090813.1353-2-jszhang@kernel.org> (raw)
In-Reply-To: <20230827090813.1353-1-jszhang@kernel.org>

From: Icenowy Zheng <uwu@icenowy.me>

The dcache.cva encoding shown in the comments are wrong, it's for
dcache.cval1 (which is restricted to L1) instead.

Fix this in the comment and in the hardcoded instruction.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
 arch/riscv/include/asm/errata_list.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index fb1a810f3d8c..feab334dd832 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE(						\
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01001      rs1       000      00000  0001011
  * dcache.cva rs1 (clean, virtual address)
- *   0000001    00100      rs1       000      00000  0001011
+ *   0000001    00101      rs1       000      00000  0001011
  *
  * dcache.cipa rs1 (clean then invalidate, physical address)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
@@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE(						\
  *   0000000    11001     00000      000      00000  0001011
  */
 #define THEAD_inval_A0	".long 0x0265000b"
-#define THEAD_clean_A0	".long 0x0245000b"
+#define THEAD_clean_A0	".long 0x0255000b"
 #define THEAD_flush_A0	".long 0x0275000b"
 #define THEAD_SYNC_S	".long 0x0190000b"
 
-- 
2.40.1


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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Icenowy Zheng <uwu@icenowy.me>,
	Sergey Matyukevich <sergey.matyukevich@syntacore.com>,
	Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding
Date: Sun, 27 Aug 2023 17:08:12 +0800	[thread overview]
Message-ID: <20230827090813.1353-2-jszhang@kernel.org> (raw)
In-Reply-To: <20230827090813.1353-1-jszhang@kernel.org>

From: Icenowy Zheng <uwu@icenowy.me>

The dcache.cva encoding shown in the comments are wrong, it's for
dcache.cval1 (which is restricted to L1) instead.

Fix this in the comment and in the hardcoded instruction.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
 arch/riscv/include/asm/errata_list.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index fb1a810f3d8c..feab334dd832 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE(						\
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
  *   0000001    01001      rs1       000      00000  0001011
  * dcache.cva rs1 (clean, virtual address)
- *   0000001    00100      rs1       000      00000  0001011
+ *   0000001    00101      rs1       000      00000  0001011
  *
  * dcache.cipa rs1 (clean then invalidate, physical address)
  * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
@@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE(						\
  *   0000000    11001     00000      000      00000  0001011
  */
 #define THEAD_inval_A0	".long 0x0265000b"
-#define THEAD_clean_A0	".long 0x0245000b"
+#define THEAD_clean_A0	".long 0x0255000b"
 #define THEAD_flush_A0	".long 0x0275000b"
 #define THEAD_SYNC_S	".long 0x0190000b"
 
-- 
2.40.1


  reply	other threads:[~2023-08-27  9:20 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-27  9:08 [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
2023-08-27  9:08 ` Jisheng Zhang
2023-08-27  9:08 ` Jisheng Zhang [this message]
2023-08-27  9:08   ` [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding Jisheng Zhang
2023-09-04 19:43   ` Drew Fustini
2023-09-04 19:43     ` Drew Fustini
2023-09-04 19:59     ` Drew Fustini
2023-09-04 19:59       ` Drew Fustini
2023-08-27  9:08 ` [PATCH v2 2/2] riscv: errata: prefix T-Head mnemonics with th Jisheng Zhang
2023-08-27  9:08   ` Jisheng Zhang
2023-08-27 10:18   ` Guo Ren
2023-08-27 10:18     ` Guo Ren
2023-08-27 11:21 ` [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
2023-08-27 11:21   ` Jisheng Zhang
2023-09-13  0:37 ` patchwork-bot+linux-riscv
2023-09-13  0:37   ` patchwork-bot+linux-riscv
2023-11-02 20:20 ` patchwork-bot+linux-riscv
2023-11-02 20:20   ` patchwork-bot+linux-riscv

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