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From: Andrzej Hajda <andrzej.hajda@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Andrzej Hajda <andrzej.hajda@intel.com>,
	Nirmoy Das <nirmoy.das@intel.com>
Subject: [Intel-gfx] [PATCH] drm/i915/gt: skip WA verfication for GEN7_MISCCPCTL on DG2
Date: Tue, 12 Sep 2023 09:35:21 +0200	[thread overview]
Message-ID: <20230912073521.2106162-1-andrzej.hajda@intel.com> (raw)

Some DG2 firmware locks this register for modification. Using wa_add
with read_mask 0 allows to skip checks of such registers.

Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 70071ead0659cc..1d1474ad945e0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1597,8 +1597,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 	/* Wa_14014830051:dg2 */
 	wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
 
-	/* Wa_14015795083 */
-	wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
+	/* Wa_14015795083
+	 * Skip verification for possibly locked register.
+	 */
+	wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,
+	       0, 0, false);
 
 	/* Wa_18018781329 */
 	wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
-- 
2.34.1


             reply	other threads:[~2023-09-12  7:35 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-12  7:35 Andrzej Hajda [this message]
2023-09-12  8:04 ` [Intel-gfx] [PATCH] drm/i915/gt: skip WA verfication for GEN7_MISCCPCTL on DG2 Andrzej Hajda
2023-09-12 16:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-09-12 16:32 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-09-12 20:08 ` [Intel-gfx] [PATCH] " Nirmoy Das
2023-09-12 21:05 ` Matt Roper
2023-09-13 10:21   ` Andrzej Hajda
2023-09-18 16:56 ` Andi Shyti

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