From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, suraj.kandpal@intel.com, ankit.k.nautiyal@intel.com, swati2.sharma@intel.com Subject: [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size Date: Tue, 12 Sep 2023 22:07:33 +0530 [thread overview] Message-ID: <20230912163735.1075868-7-mitulkumar.ajitkumar.golani@intel.com> (raw) In-Reply-To: <20230912163735.1075868-1-mitulkumar.ajitkumar.golani@intel.com> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> This patch adds support to iterate over compressed output bpp as per the fractional step, supported by DP sink. v2: -Avoid ending up with compressed bpp, same as pipe bpp. (Stan) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 37 +++++++++++++++---------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a359a8d65dbd..25d033622439 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1716,15 +1716,15 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); } -static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock, +static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock, u32 lane_count, u32 mode_clock, enum intel_output_format output_format, int timeslots) { u32 available_bw, required_bw; - available_bw = (link_clock * lane_count * timeslots) / 8; - required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock)); + available_bw = (link_clock * lane_count * timeslots * 16) / 8; + required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock)); return available_bw > required_bw; } @@ -1732,7 +1732,7 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock, static int dsc_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, - u16 compressed_bpp, + u16 compressed_bppx16, int timeslots) { const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; @@ -1747,8 +1747,8 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, for (lane_count = limits->min_lane_count; lane_count <= limits->max_lane_count; lane_count <<= 1) { - if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count, - adjusted_mode->clock, + if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate, + lane_count, adjusted_mode->clock, pipe_config->output_format, timeslots)) continue; @@ -1861,7 +1861,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp, ret = dsc_compute_link_config(intel_dp, pipe_config, limits, - valid_dsc_bpp[i], + valid_dsc_bpp[i] << 4, timeslots); if (ret == 0) { pipe_config->dsc.compressed_bpp_x16 = intel_fractional_bpp_to_x16(valid_dsc_bpp[i]); @@ -1887,22 +1887,31 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, int pipe_bpp, int timeslots) { - u16 compressed_bpp; + u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd); + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + u16 compressed_bppx16; + u8 bppx16_step; int ret; + if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1) + bppx16_step = 16; + else + bppx16_step = 16 / bppx16_incr; + /* Compressed BPP should be less than the Input DSC bpp */ - dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); + dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step); + dsc_min_bpp = dsc_min_bpp << 4; - for (compressed_bpp = dsc_max_bpp; - compressed_bpp >= dsc_min_bpp; - compressed_bpp--) { + for (compressed_bppx16 = dsc_max_bpp; + compressed_bppx16 >= dsc_min_bpp; + compressed_bppx16 -= bppx16_step) { ret = dsc_compute_link_config(intel_dp, pipe_config, limits, - compressed_bpp, + compressed_bppx16, timeslots); if (ret == 0) { - pipe_config->dsc.compressed_bpp_x16 = intel_fractional_bpp_to_x16(compressed_bpp); + pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16; return 0; } } -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [Intel-gfx] [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size Date: Tue, 12 Sep 2023 22:07:33 +0530 [thread overview] Message-ID: <20230912163735.1075868-7-mitulkumar.ajitkumar.golani@intel.com> (raw) In-Reply-To: <20230912163735.1075868-1-mitulkumar.ajitkumar.golani@intel.com> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> This patch adds support to iterate over compressed output bpp as per the fractional step, supported by DP sink. v2: -Avoid ending up with compressed bpp, same as pipe bpp. (Stan) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 37 +++++++++++++++---------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a359a8d65dbd..25d033622439 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1716,15 +1716,15 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); } -static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock, +static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock, u32 lane_count, u32 mode_clock, enum intel_output_format output_format, int timeslots) { u32 available_bw, required_bw; - available_bw = (link_clock * lane_count * timeslots) / 8; - required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock)); + available_bw = (link_clock * lane_count * timeslots * 16) / 8; + required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock)); return available_bw > required_bw; } @@ -1732,7 +1732,7 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock, static int dsc_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, - u16 compressed_bpp, + u16 compressed_bppx16, int timeslots) { const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; @@ -1747,8 +1747,8 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, for (lane_count = limits->min_lane_count; lane_count <= limits->max_lane_count; lane_count <<= 1) { - if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count, - adjusted_mode->clock, + if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate, + lane_count, adjusted_mode->clock, pipe_config->output_format, timeslots)) continue; @@ -1861,7 +1861,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp, ret = dsc_compute_link_config(intel_dp, pipe_config, limits, - valid_dsc_bpp[i], + valid_dsc_bpp[i] << 4, timeslots); if (ret == 0) { pipe_config->dsc.compressed_bpp_x16 = intel_fractional_bpp_to_x16(valid_dsc_bpp[i]); @@ -1887,22 +1887,31 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, int pipe_bpp, int timeslots) { - u16 compressed_bpp; + u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd); + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + u16 compressed_bppx16; + u8 bppx16_step; int ret; + if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1) + bppx16_step = 16; + else + bppx16_step = 16 / bppx16_incr; + /* Compressed BPP should be less than the Input DSC bpp */ - dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); + dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step); + dsc_min_bpp = dsc_min_bpp << 4; - for (compressed_bpp = dsc_max_bpp; - compressed_bpp >= dsc_min_bpp; - compressed_bpp--) { + for (compressed_bppx16 = dsc_max_bpp; + compressed_bppx16 >= dsc_min_bpp; + compressed_bppx16 -= bppx16_step) { ret = dsc_compute_link_config(intel_dp, pipe_config, limits, - compressed_bpp, + compressed_bppx16, timeslots); if (ret == 0) { - pipe_config->dsc.compressed_bpp_x16 = intel_fractional_bpp_to_x16(compressed_bpp); + pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16; return 0; } } -- 2.25.1
next prev parent reply other threads:[~2023-09-12 16:43 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-09-12 16:37 [PATCH 0/8] Add DSC fractional bpp support Mitul Golani 2023-09-12 16:37 ` [Intel-gfx] " Mitul Golani 2023-09-12 16:37 ` [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision Mitul Golani 2023-09-12 16:37 ` [Intel-gfx] " Mitul Golani 2023-09-13 4:37 ` Kandpal, Suraj 2023-09-13 4:37 ` [Intel-gfx] " Kandpal, Suraj 2023-09-12 16:37 ` [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format Mitul Golani 2023-09-12 16:37 ` [Intel-gfx] " Mitul Golani 2023-09-13 4:42 ` Kandpal, Suraj 2023-09-13 4:42 ` [Intel-gfx] " Kandpal, Suraj 2023-09-12 16:37 ` [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values Mitul Golani 2023-09-12 16:37 ` [Intel-gfx] " Mitul Golani 2023-09-12 16:37 ` [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data Mitul Golani 2023-09-12 16:37 ` [Intel-gfx] " Mitul Golani 2023-09-12 16:37 ` [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp Mitul Golani 2023-09-12 16:37 ` [Intel-gfx] " Mitul Golani 2023-09-12 16:37 ` Mitul Golani [this message] 2023-09-12 16:37 ` [Intel-gfx] [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size Mitul Golani 2023-09-12 16:37 ` [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp Mitul Golani 2023-09-12 16:37 ` [Intel-gfx] " Mitul Golani 2023-09-12 16:37 ` [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs Mitul Golani 2023-09-12 16:37 ` [Intel-gfx] " Mitul Golani 2023-09-12 22:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev6) Patchwork 2023-09-12 22:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2023-09-12 22:21 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2023-09-13 6:05 [PATCH 0/8] Add DSC fractional bpp support Mitul Golani 2023-09-13 6:06 ` [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size Mitul Golani 2023-09-26 8:23 [PATCH 0/8] Add DSC fractional bpp support Mitul Golani 2023-09-26 8:23 ` [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size Mitul Golani 2023-09-29 7:13 [PATCH 0/8] Add DSC fractional bpp support Mitul Golani 2023-09-29 7:13 ` [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size Mitul Golani
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