From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: [PATCH 6.1.y-cip 14/15] arm64: dts: renesas: r9a07g043: Add MTU3a node
Date: Tue, 12 Sep 2023 20:59:14 +0100 [thread overview]
Message-ID: <20230912195915.607664-15-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com>
commit a4c125a8a35113f53f5085b376cb9a9763fb9129 upstream.
Add MTU3a node to R9A07G043 (RZ/{G2UL,Five}) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230727081848.100834-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 27c35a657b15..8721f4c9fa0f 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -74,6 +74,76 @@ soc: soc {
#size-cells = <2>;
ranges;
+ mtu3: timer@10001200 {
+ compatible = "renesas,r9a07g043-mtu3",
+ "renesas,rz-mtu3";
+ reg = <0 0x10001200 0 0xb00>;
+ interrupts = <SOC_PERIPHERAL_IRQ(170) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(171) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(172) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(173) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(174) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(175) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(176) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(177) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(178) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(179) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(180) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(181) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(182) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(183) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(184) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(185) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(186) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(187) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(188) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(189) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(190) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(191) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(192) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(193) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(194) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(195) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(196) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(197) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(198) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(199) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(200) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(201) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(202) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(203) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(204) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(205) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(206) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(207) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(208) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(209) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(210) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(211) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(212) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(213) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
+ "tciv0", "tgie0", "tgif0",
+ "tgia1", "tgib1", "tciv1", "tciu1",
+ "tgia2", "tgib2", "tciv2", "tciu2",
+ "tgia3", "tgib3", "tgic3", "tgid3",
+ "tciv3",
+ "tgia4", "tgib4", "tgic4", "tgid4",
+ "tciv4",
+ "tgiu5", "tgiv5", "tgiw5",
+ "tgia6", "tgib6", "tgic6", "tgid6",
+ "tciv6",
+ "tgia7", "tgib7", "tgic7", "tgid7",
+ "tciv7",
+ "tgia8", "tgib8", "tgic8", "tgid8",
+ "tciv8", "tciu8";
+ clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
--
2.25.1
next prev parent reply other threads:[~2023-09-12 19:59 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-12 19:59 [PATCH 6.1.y-cip 00/15] Enable MTU3 PWM/Counter support on RZ/G2L SMARC Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 01/15] dmaengine: sh: rz-dmac: Improve cleanup order in probe()/remove() Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 02/15] dmaengine: sh: rz-dmac: Fix destination and source data size setting Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 03/15] clk: renesas: r9a07g043: Add MTU3a clock and reset entry Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 04/15] mfd: rz-mtu3: Fix COMPILE_TEST build error Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 05/15] mfd: rz-mtu3: Link time dependencies Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 06/15] mfd: rz-mtu3: Reduce critical sections Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 07/15] mfd: rz-mtu3: Replace raw_spin_lock->spin_lock() Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 08/15] Documentation: ABI: sysfs-bus-counter: Fix indentation Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 09/15] counter: rz-mtu3-cnt: Reorder locking sequence for consistency Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 10/15] pwm: rz-mtu3: Fix build warning 'num_channel_ios' not described Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 11/15] arm64: defconfig: Enable Renesas MTU3a PWM config Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 12/15] arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3 Biju Das
2023-09-12 19:59 ` [PATCH 6.1.y-cip 13/15] arm64: dts: renesas: rzg2lc-smarc: " Biju Das
2023-09-12 19:59 ` Biju Das [this message]
2023-09-12 19:59 ` [PATCH 6.1.y-cip 15/15] arm64: dts: renesas: rzg2ul-smarc: " Biju Das
2023-09-12 21:27 ` [PATCH 6.1.y-cip 00/15] Enable MTU3 PWM/Counter support on RZ/G2L SMARC Pavel Machek
2023-09-13 15:51 ` Pavel Machek
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