From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, suraj.kandpal@intel.com, ankit.k.nautiyal@intel.com, swati2.sharma@intel.com Subject: [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values Date: Wed, 13 Sep 2023 11:36:01 +0530 [thread overview] Message-ID: <20230913060606.1105349-4-mitulkumar.ajitkumar.golani@intel.com> (raw) In-Reply-To: <20230913060606.1105349-1-mitulkumar.ajitkumar.golani@intel.com> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate this precision while computing m_n values. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 6 +++++- drivers/gpu/drm/i915/display/intel_display.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 5 +++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++++-- drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- 5 files changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index afcbdd4f105a..b37aeac961f4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2380,10 +2380,14 @@ void intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, - bool fec_enable) + bool fec_enable, + bool is_dsc_fractional_bpp) { u32 data_clock = bits_per_pixel * pixel_clock; + if (is_dsc_fractional_bpp) + data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16); + if (fec_enable) data_clock = intel_dp_mode_to_fec_clock(data_clock); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 49ac8473b988..a4c4ca3cad65 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state, void intel_link_compute_m_n(u16 bpp, int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, - bool fec_enable); + bool fec_enable, bool is_dsc_fractional_bpp); u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, u32 pixel_format, u64 modifier); enum drm_mode_status diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index cb647bb38b12..6e09e21909a1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2562,7 +2562,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock, pipe_config->port_clock, &pipe_config->dp_m2_n2, - pipe_config->fec_enable); + pipe_config->fec_enable, false); /* FIXME: abstract this better */ if (pipe_config->splitter.enable) @@ -2741,7 +2741,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, adjusted_mode->crtc_clock, pipe_config->port_clock, &pipe_config->dp_m_n, - pipe_config->fec_enable); + pipe_config->fec_enable, + pipe_config->dsc.compression_enable); /* FIXME: abstract this better */ if (pipe_config->splitter.enable) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 7bf0b6e4ac0b..8f6bd54532cb 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -172,7 +172,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, adjusted_mode->crtc_clock, crtc_state->port_clock, &crtc_state->dp_m_n, - crtc_state->fec_enable); + crtc_state->fec_enable, + false); crtc_state->dp_m_n.tu = slots; return 0; @@ -269,7 +270,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, adjusted_mode->crtc_clock, crtc_state->port_clock, &crtc_state->dp_m_n, - crtc_state->fec_enable); + crtc_state->fec_enable, + crtc_state->dsc.compression_enable); crtc_state->dp_m_n.tu = slots; return 0; diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index e12b46a84fa1..15fddabf7c2e 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc, pipe_config->fdi_lanes = lane; intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, - link_bw, &pipe_config->fdi_m_n, false); + link_bw, &pipe_config->fdi_m_n, false, false); ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config); if (ret == -EDEADLK) -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values Date: Wed, 13 Sep 2023 11:36:01 +0530 [thread overview] Message-ID: <20230913060606.1105349-4-mitulkumar.ajitkumar.golani@intel.com> (raw) In-Reply-To: <20230913060606.1105349-1-mitulkumar.ajitkumar.golani@intel.com> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com> MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate this precision while computing m_n values. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 6 +++++- drivers/gpu/drm/i915/display/intel_display.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 5 +++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++++-- drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- 5 files changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index afcbdd4f105a..b37aeac961f4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2380,10 +2380,14 @@ void intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, - bool fec_enable) + bool fec_enable, + bool is_dsc_fractional_bpp) { u32 data_clock = bits_per_pixel * pixel_clock; + if (is_dsc_fractional_bpp) + data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16); + if (fec_enable) data_clock = intel_dp_mode_to_fec_clock(data_clock); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 49ac8473b988..a4c4ca3cad65 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state, void intel_link_compute_m_n(u16 bpp, int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, - bool fec_enable); + bool fec_enable, bool is_dsc_fractional_bpp); u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, u32 pixel_format, u64 modifier); enum drm_mode_status diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index cb647bb38b12..6e09e21909a1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2562,7 +2562,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock, pipe_config->port_clock, &pipe_config->dp_m2_n2, - pipe_config->fec_enable); + pipe_config->fec_enable, false); /* FIXME: abstract this better */ if (pipe_config->splitter.enable) @@ -2741,7 +2741,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, adjusted_mode->crtc_clock, pipe_config->port_clock, &pipe_config->dp_m_n, - pipe_config->fec_enable); + pipe_config->fec_enable, + pipe_config->dsc.compression_enable); /* FIXME: abstract this better */ if (pipe_config->splitter.enable) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 7bf0b6e4ac0b..8f6bd54532cb 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -172,7 +172,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, adjusted_mode->crtc_clock, crtc_state->port_clock, &crtc_state->dp_m_n, - crtc_state->fec_enable); + crtc_state->fec_enable, + false); crtc_state->dp_m_n.tu = slots; return 0; @@ -269,7 +270,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, adjusted_mode->crtc_clock, crtc_state->port_clock, &crtc_state->dp_m_n, - crtc_state->fec_enable); + crtc_state->fec_enable, + crtc_state->dsc.compression_enable); crtc_state->dp_m_n.tu = slots; return 0; diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index e12b46a84fa1..15fddabf7c2e 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc, pipe_config->fdi_lanes = lane; intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, - link_bw, &pipe_config->fdi_m_n, false); + link_bw, &pipe_config->fdi_m_n, false, false); ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config); if (ret == -EDEADLK) -- 2.25.1
next prev parent reply other threads:[~2023-09-13 6:12 UTC|newest] Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-09-13 6:05 [PATCH 0/8] Add DSC fractional bpp support Mitul Golani 2023-09-13 6:05 ` [Intel-gfx] " Mitul Golani 2023-09-13 6:05 ` [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision Mitul Golani 2023-09-13 6:05 ` [Intel-gfx] " Mitul Golani 2023-09-13 6:14 ` Kandpal, Suraj 2023-09-13 6:14 ` [Intel-gfx] " Kandpal, Suraj 2023-09-21 7:41 ` Jani Nikula 2023-09-21 7:41 ` [Intel-gfx] " Jani Nikula 2023-09-22 12:05 ` Maxime Ripard 2023-09-22 12:05 ` [Intel-gfx] " Maxime Ripard 2023-09-22 14:39 ` [1/8] " Sui Jingfeng 2023-09-22 14:39 ` [Intel-gfx] " Sui Jingfeng 2023-09-13 6:06 ` [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format Mitul Golani 2023-09-13 6:06 ` [Intel-gfx] " Mitul Golani 2023-09-22 16:02 ` [2/8] " Sui Jingfeng 2023-09-22 16:02 ` [Intel-gfx] " Sui Jingfeng 2023-09-13 6:06 ` Mitul Golani [this message] 2023-09-13 6:06 ` [Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values Mitul Golani 2023-09-22 15:12 ` [3/8] " Sui Jingfeng 2023-09-22 15:12 ` [Intel-gfx] " Sui Jingfeng 2023-09-13 6:06 ` [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data Mitul Golani 2023-09-13 6:06 ` [Intel-gfx] " Mitul Golani 2023-09-13 6:06 ` [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp Mitul Golani 2023-09-13 6:06 ` [Intel-gfx] " Mitul Golani 2023-09-13 6:06 ` [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size Mitul Golani 2023-09-13 6:06 ` [Intel-gfx] " Mitul Golani 2023-09-13 6:06 ` [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp Mitul Golani 2023-09-13 6:06 ` [Intel-gfx] " Mitul Golani 2023-09-21 8:00 ` Jani Nikula 2023-09-21 8:00 ` [Intel-gfx] " Jani Nikula 2023-09-21 11:53 ` Sharma, Swati2 2023-09-21 11:53 ` [Intel-gfx] " Sharma, Swati2 2023-09-21 12:14 ` Jani Nikula 2023-09-21 12:14 ` [Intel-gfx] " Jani Nikula 2023-09-21 12:59 ` Sharma, Swati2 2023-09-21 12:59 ` [Intel-gfx] " Sharma, Swati2 2023-09-22 12:28 ` Jani Nikula 2023-09-22 12:28 ` [Intel-gfx] " Jani Nikula 2023-09-22 16:03 ` [7/8] " Sui Jingfeng 2023-09-22 16:03 ` [Intel-gfx] " Sui Jingfeng 2023-09-13 6:06 ` [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs Mitul Golani 2023-09-13 6:06 ` [Intel-gfx] " Mitul Golani 2023-09-13 6:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev7) Patchwork 2023-09-13 6:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2023-09-13 6:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-09-13 8:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2023-09-20 4:56 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork 2023-09-22 12:45 ` [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Imre Deak 2023-09-27 15:22 ` Imre Deak 2023-09-27 16:36 ` Sharma, Swati2 -- strict thread matches above, loose matches on Subject: below -- 2023-09-29 7:13 Mitul Golani 2023-09-29 7:13 ` [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values Mitul Golani 2023-09-26 8:23 [PATCH 0/8] Add DSC fractional bpp support Mitul Golani 2023-09-26 8:23 ` [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values Mitul Golani 2023-09-12 16:37 [PATCH 0/8] Add DSC fractional bpp support Mitul Golani 2023-09-12 16:37 ` [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values Mitul Golani
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