From: Joey Gouly <joey.gouly@arm.com> To: <linux-arm-kernel@lists.infradead.org> Cc: <nd@arm.com>, <akpm@linux-foundation.org>, <aneesh.kumar@linux.ibm.com>, <catalin.marinas@arm.com>, <dave.hansen@linux.intel.com>, <joey.gouly@arm.com>, <maz@kernel.org>, <oliver.upton@linux.dev>, <shuah@kernel.org>, <will@kernel.org>, <kvmarm@lists.linux.dev>, <linux-fsdevel@vger.kernel.org>, <linux-mm@kvack.org>, <linux-kselftest@vger.kernel.org> Subject: [PATCH v1 15/20] arm64: add POE signal support Date: Wed, 27 Sep 2023 15:01:18 +0100 [thread overview] Message-ID: <20230927140123.5283-16-joey.gouly@arm.com> (raw) In-Reply-To: <20230927140123.5283-1-joey.gouly@arm.com> Add PKEY support to signals, by saving and restoring POR_EL0 from the stackframe. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> --- arch/arm64/include/uapi/asm/sigcontext.h | 7 ++++ arch/arm64/kernel/signal.c | 51 ++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h index f23c1dc3f002..cef85eeaf541 100644 --- a/arch/arm64/include/uapi/asm/sigcontext.h +++ b/arch/arm64/include/uapi/asm/sigcontext.h @@ -98,6 +98,13 @@ struct esr_context { __u64 esr; }; +#define POE_MAGIC 0x504f4530 + +struct poe_context { + struct _aarch64_ctx head; + __u64 por_el0; +}; + /* * extra_context: describes extra space in the signal frame for * additional structures that don't fit in sigcontext.__reserved[]. diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index 0e8beb3349ea..3517271ae0dc 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -62,6 +62,7 @@ struct rt_sigframe_user_layout { unsigned long zt_offset; unsigned long extra_offset; unsigned long end_offset; + unsigned long poe_offset; }; #define BASE_SIGFRAME_SIZE round_up(sizeof(struct rt_sigframe), 16) @@ -182,6 +183,8 @@ struct user_ctxs { u32 za_size; struct zt_context __user *zt; u32 zt_size; + struct poe_context __user *poe; + u32 poe_size; }; static int preserve_fpsimd_context(struct fpsimd_context __user *ctx) @@ -227,6 +230,20 @@ static int restore_fpsimd_context(struct user_ctxs *user) return err ? -EFAULT : 0; } +static int restore_poe_context(struct user_ctxs *user) +{ + u64 por_el0; + int err = 0; + + if (user->poe_size != sizeof(*user->poe)) + return -EINVAL; + + __get_user_error(por_el0, &(user->poe->por_el0), err); + if (!err) + write_sysreg_s(por_el0, SYS_POR_EL0); + + return err; +} #ifdef CONFIG_ARM64_SVE @@ -590,6 +607,7 @@ static int parse_user_sigframe(struct user_ctxs *user, user->tpidr2 = NULL; user->za = NULL; user->zt = NULL; + user->poe = NULL; if (!IS_ALIGNED((unsigned long)base, 16)) goto invalid; @@ -640,6 +658,17 @@ static int parse_user_sigframe(struct user_ctxs *user, /* ignore */ break; + case POE_MAGIC: + if (!cpus_have_final_cap(ARM64_HAS_S1POE)) + goto invalid; + + if (user->poe) + goto invalid; + + user->poe = (struct poe_context __user *)head; + user->poe_size = size; + break; + case SVE_MAGIC: if (!system_supports_sve() && !system_supports_sme()) goto invalid; @@ -812,6 +841,9 @@ static int restore_sigframe(struct pt_regs *regs, if (err == 0 && system_supports_sme2() && user.zt) err = restore_zt_context(&user); + if (err == 0 && cpus_have_final_cap(ARM64_HAS_S1POE) && user.poe) + err = restore_poe_context(&user); + return err; } @@ -928,6 +960,13 @@ static int setup_sigframe_layout(struct rt_sigframe_user_layout *user, } } + if (cpus_have_const_cap(ARM64_HAS_S1POE)) { + err = sigframe_alloc(user, &user->poe_offset, + sizeof(struct poe_context)); + if (err) + return err; + } + return sigframe_alloc_end(user); } @@ -968,6 +1007,15 @@ static int setup_sigframe(struct rt_sigframe_user_layout *user, __put_user_error(current->thread.fault_code, &esr_ctx->esr, err); } + if (cpus_have_final_cap(ARM64_HAS_S1POE) && err == 0 && user->poe_offset) { + struct poe_context __user *poe_ctx = + apply_user_offset(user, user->poe_offset); + + __put_user_error(POE_MAGIC, &poe_ctx->head.magic, err); + __put_user_error(sizeof(*poe_ctx), &poe_ctx->head.size, err); + __put_user_error(read_sysreg_s(SYS_POR_EL0), &poe_ctx->por_el0, err); + } + /* Scalable Vector Extension state (including streaming), if present */ if ((system_supports_sve() || system_supports_sme()) && err == 0 && user->sve_offset) { @@ -1119,6 +1167,9 @@ static void setup_return(struct pt_regs *regs, struct k_sigaction *ka, sme_smstop(); } + if (cpus_have_final_cap(ARM64_HAS_S1POE)) + write_sysreg_s(POR_EL0_INIT, SYS_POR_EL0); + if (ka->sa.sa_flags & SA_RESTORER) sigtramp = ka->sa.sa_restorer; else -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Joey Gouly <joey.gouly@arm.com> To: <linux-arm-kernel@lists.infradead.org> Cc: <nd@arm.com>, <akpm@linux-foundation.org>, <aneesh.kumar@linux.ibm.com>, <catalin.marinas@arm.com>, <dave.hansen@linux.intel.com>, <joey.gouly@arm.com>, <maz@kernel.org>, <oliver.upton@linux.dev>, <shuah@kernel.org>, <will@kernel.org>, <kvmarm@lists.linux.dev>, <linux-fsdevel@vger.kernel.org>, <linux-mm@kvack.org>, <linux-kselftest@vger.kernel.org> Subject: [PATCH v1 15/20] arm64: add POE signal support Date: Wed, 27 Sep 2023 15:01:18 +0100 [thread overview] Message-ID: <20230927140123.5283-16-joey.gouly@arm.com> (raw) In-Reply-To: <20230927140123.5283-1-joey.gouly@arm.com> Add PKEY support to signals, by saving and restoring POR_EL0 from the stackframe. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> --- arch/arm64/include/uapi/asm/sigcontext.h | 7 ++++ arch/arm64/kernel/signal.c | 51 ++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h index f23c1dc3f002..cef85eeaf541 100644 --- a/arch/arm64/include/uapi/asm/sigcontext.h +++ b/arch/arm64/include/uapi/asm/sigcontext.h @@ -98,6 +98,13 @@ struct esr_context { __u64 esr; }; +#define POE_MAGIC 0x504f4530 + +struct poe_context { + struct _aarch64_ctx head; + __u64 por_el0; +}; + /* * extra_context: describes extra space in the signal frame for * additional structures that don't fit in sigcontext.__reserved[]. diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index 0e8beb3349ea..3517271ae0dc 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -62,6 +62,7 @@ struct rt_sigframe_user_layout { unsigned long zt_offset; unsigned long extra_offset; unsigned long end_offset; + unsigned long poe_offset; }; #define BASE_SIGFRAME_SIZE round_up(sizeof(struct rt_sigframe), 16) @@ -182,6 +183,8 @@ struct user_ctxs { u32 za_size; struct zt_context __user *zt; u32 zt_size; + struct poe_context __user *poe; + u32 poe_size; }; static int preserve_fpsimd_context(struct fpsimd_context __user *ctx) @@ -227,6 +230,20 @@ static int restore_fpsimd_context(struct user_ctxs *user) return err ? -EFAULT : 0; } +static int restore_poe_context(struct user_ctxs *user) +{ + u64 por_el0; + int err = 0; + + if (user->poe_size != sizeof(*user->poe)) + return -EINVAL; + + __get_user_error(por_el0, &(user->poe->por_el0), err); + if (!err) + write_sysreg_s(por_el0, SYS_POR_EL0); + + return err; +} #ifdef CONFIG_ARM64_SVE @@ -590,6 +607,7 @@ static int parse_user_sigframe(struct user_ctxs *user, user->tpidr2 = NULL; user->za = NULL; user->zt = NULL; + user->poe = NULL; if (!IS_ALIGNED((unsigned long)base, 16)) goto invalid; @@ -640,6 +658,17 @@ static int parse_user_sigframe(struct user_ctxs *user, /* ignore */ break; + case POE_MAGIC: + if (!cpus_have_final_cap(ARM64_HAS_S1POE)) + goto invalid; + + if (user->poe) + goto invalid; + + user->poe = (struct poe_context __user *)head; + user->poe_size = size; + break; + case SVE_MAGIC: if (!system_supports_sve() && !system_supports_sme()) goto invalid; @@ -812,6 +841,9 @@ static int restore_sigframe(struct pt_regs *regs, if (err == 0 && system_supports_sme2() && user.zt) err = restore_zt_context(&user); + if (err == 0 && cpus_have_final_cap(ARM64_HAS_S1POE) && user.poe) + err = restore_poe_context(&user); + return err; } @@ -928,6 +960,13 @@ static int setup_sigframe_layout(struct rt_sigframe_user_layout *user, } } + if (cpus_have_const_cap(ARM64_HAS_S1POE)) { + err = sigframe_alloc(user, &user->poe_offset, + sizeof(struct poe_context)); + if (err) + return err; + } + return sigframe_alloc_end(user); } @@ -968,6 +1007,15 @@ static int setup_sigframe(struct rt_sigframe_user_layout *user, __put_user_error(current->thread.fault_code, &esr_ctx->esr, err); } + if (cpus_have_final_cap(ARM64_HAS_S1POE) && err == 0 && user->poe_offset) { + struct poe_context __user *poe_ctx = + apply_user_offset(user, user->poe_offset); + + __put_user_error(POE_MAGIC, &poe_ctx->head.magic, err); + __put_user_error(sizeof(*poe_ctx), &poe_ctx->head.size, err); + __put_user_error(read_sysreg_s(SYS_POR_EL0), &poe_ctx->por_el0, err); + } + /* Scalable Vector Extension state (including streaming), if present */ if ((system_supports_sve() || system_supports_sme()) && err == 0 && user->sve_offset) { @@ -1119,6 +1167,9 @@ static void setup_return(struct pt_regs *regs, struct k_sigaction *ka, sme_smstop(); } + if (cpus_have_final_cap(ARM64_HAS_S1POE)) + write_sysreg_s(POR_EL0_INIT, SYS_POR_EL0); + if (ka->sa.sa_flags & SA_RESTORER) sigtramp = ka->sa.sa_restorer; else -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-09-27 14:04 UTC|newest] Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-09-27 14:01 [PATCH v1 00/20] Permission Overlay Extension Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-27 14:01 ` [PATCH v1 01/20] arm64/sysreg: add system register POR_EL{0,1} Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-10-05 14:03 ` Mark Brown 2023-10-05 14:03 ` Mark Brown 2023-09-27 14:01 ` [PATCH v1 02/20] arm64/sysreg: update CPACR_EL1 register Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-10-05 14:02 ` Mark Brown 2023-10-05 14:02 ` Mark Brown 2023-09-27 14:01 ` [PATCH v1 03/20] arm64: cpufeature: add Permission Overlay Extension cpucap Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-27 14:01 ` [PATCH v1 04/20] arm64: disable trapping of POR_EL0 to EL2 Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-27 14:01 ` [PATCH v1 05/20] arm64: context switch POR_EL0 register Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-10-04 16:49 ` Catalin Marinas 2023-10-04 16:49 ` Catalin Marinas 2023-10-05 14:14 ` Mark Brown 2023-10-05 14:14 ` Mark Brown 2023-10-10 9:54 ` Joey Gouly 2023-10-10 9:54 ` Joey Gouly 2023-10-10 11:47 ` Mark Brown 2023-10-10 11:47 ` Mark Brown 2023-09-27 14:01 ` [PATCH v1 06/20] KVM: arm64: Save/restore POE registers Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-28 16:47 ` Oliver Upton 2023-09-28 16:47 ` Oliver Upton 2023-09-27 14:01 ` [PATCH v1 07/20] arm64: enable the Permission Overlay Extension for EL0 Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-10-05 14:17 ` Mark Brown 2023-10-05 14:17 ` Mark Brown 2023-10-05 14:19 ` Mark Brown 2023-10-05 14:19 ` Mark Brown 2023-09-27 14:01 ` [PATCH v1 08/20] arm64: add POIndex defines Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-27 14:01 ` [PATCH v1 09/20] arm64: define VM_PKEY_BIT* for arm64 Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-30 11:57 ` kernel test robot 2023-09-30 11:57 ` kernel test robot 2023-10-03 16:51 ` Dave Hansen 2023-10-03 16:51 ` Dave Hansen 2023-09-27 14:01 ` [PATCH v1 10/20] arm64: mask out POIndex when modifying a PTE Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-27 14:01 ` [PATCH v1 11/20] arm64: enable ARCH_HAS_PKEYS on arm64 Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-30 13:05 ` kernel test robot 2023-09-30 13:05 ` kernel test robot 2023-09-27 14:01 ` [PATCH v1 12/20] arm64: handle PKEY/POE faults Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-27 14:01 ` [PATCH v1 13/20] arm64: stop using generic mm_hooks.h Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-27 14:01 ` [PATCH v1 14/20] arm64: implement PKEYS support Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-27 14:01 ` Joey Gouly [this message] 2023-09-27 14:01 ` [PATCH v1 15/20] arm64: add POE signal support Joey Gouly 2023-10-05 14:34 ` Mark Brown 2023-10-05 14:34 ` Mark Brown 2023-10-09 14:49 ` Mark Brown 2023-10-09 14:49 ` Mark Brown 2023-10-10 9:58 ` Joey Gouly 2023-10-10 9:58 ` Joey Gouly 2023-10-10 11:48 ` Mark Brown 2023-10-10 11:48 ` Mark Brown 2023-10-10 9:57 ` Joey Gouly 2023-10-10 9:57 ` Joey Gouly 2023-10-10 11:56 ` Mark Brown 2023-10-10 11:56 ` Mark Brown 2023-09-27 14:01 ` [PATCH v1 16/20] arm64: enable PKEY support for CPUs with S1POE Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-27 14:01 ` [PATCH v1 17/20] arm64: enable POE and PIE to coexist Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-27 14:01 ` [PATCH v1 18/20] kselftest/arm64: move get_header() Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-09-27 14:01 ` [PATCH v1 19/20] selftests: mm: move fpregs printing Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-10-03 16:46 ` Dave Hansen 2023-10-03 16:46 ` Dave Hansen 2023-09-27 14:01 ` [PATCH v1 20/20] selftests: mm: make protection_keys test work on arm64 Joey Gouly 2023-09-27 14:01 ` Joey Gouly 2023-10-03 16:46 ` Dave Hansen 2023-10-03 16:46 ` Dave Hansen
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