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From: Prabhakar <prabhakar.csengg@gmail.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 1/5] riscv: dts: renesas: r9a07g043f: Add L2 cache node
Date: Fri, 29 Sep 2023 01:07:00 +0100	[thread overview]
Message-ID: <20230929000704.53217-2-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add L2 cache node for RZ/Five SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 6ec1c6f9a403..c8d63a8f7d86 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -29,6 +29,7 @@ cpu0: cpu@0 {
 			i-cache-line-size = <0x40>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <0x40>;
+			next-level-cache = <&l2cache>;
 			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
 			operating-points-v2 = <&cluster0_opp>;
 
@@ -56,4 +57,15 @@ plic: interrupt-controller@12c00000 {
 		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
 		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
 	};
+
+	l2cache: cache-controller@13400000 {
+		compatible = "andestech,ax45mp-cache", "cache";
+		reg = <0x0 0x13400000 0x0 0x100000>;
+		interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
+		cache-size = <0x40000>;
+		cache-line-size = <64>;
+		cache-sets = <1024>;
+		cache-unified;
+		cache-level = <2>;
+	};
 };
-- 
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: Prabhakar <prabhakar.csengg@gmail.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 1/5] riscv: dts: renesas: r9a07g043f: Add L2 cache node
Date: Fri, 29 Sep 2023 01:07:00 +0100	[thread overview]
Message-ID: <20230929000704.53217-2-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add L2 cache node for RZ/Five SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 6ec1c6f9a403..c8d63a8f7d86 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -29,6 +29,7 @@ cpu0: cpu@0 {
 			i-cache-line-size = <0x40>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <0x40>;
+			next-level-cache = <&l2cache>;
 			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
 			operating-points-v2 = <&cluster0_opp>;
 
@@ -56,4 +57,15 @@ plic: interrupt-controller@12c00000 {
 		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
 		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
 	};
+
+	l2cache: cache-controller@13400000 {
+		compatible = "andestech,ax45mp-cache", "cache";
+		reg = <0x0 0x13400000 0x0 0x100000>;
+		interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
+		cache-size = <0x40000>;
+		cache-line-size = <64>;
+		cache-sets = <1024>;
+		cache-unified;
+		cache-level = <2>;
+	};
 };
-- 
2.34.1


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  reply	other threads:[~2023-09-29  0:07 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-29  0:06 [PATCH 0/5] Enable peripherals on RZ/Five SMARC EVK Prabhakar
2023-09-29  0:06 ` Prabhakar
2023-09-29  0:07 ` Prabhakar [this message]
2023-09-29  0:07   ` [PATCH 1/5] riscv: dts: renesas: r9a07g043f: Add L2 cache node Prabhakar
2023-10-03 12:23   ` Geert Uytterhoeven
2023-10-03 12:23     ` Geert Uytterhoeven
2023-09-29  0:07 ` [PATCH 2/5] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property Prabhakar
2023-09-29  0:07   ` Prabhakar
2023-10-03 12:24   ` Geert Uytterhoeven
2023-10-03 12:24     ` Geert Uytterhoeven
2023-09-29  0:07 ` [PATCH 3/5] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled Prabhakar
2023-09-29  0:07   ` Prabhakar
2023-10-03 12:28   ` Geert Uytterhoeven
2023-10-03 12:28     ` Geert Uytterhoeven
2023-10-03 12:37     ` Lad, Prabhakar
2023-10-03 12:37       ` Lad, Prabhakar
2023-09-29  0:07 ` [PATCH 4/5] riscv: dts: renesas: rzfive-smarc: Drop dma properties from SSI1 node Prabhakar
2023-09-29  0:07   ` Prabhakar
2023-09-29  0:30   ` Samuel Holland
2023-09-29  0:30     ` Samuel Holland
2023-09-29  8:35     ` Lad, Prabhakar
2023-09-29  8:35       ` Lad, Prabhakar
2023-09-29  0:07 ` [PATCH 5/5] riscv: configs: defconfig: Enable configs required for RZ/Five SoC Prabhakar
2023-09-29  0:07   ` Prabhakar
2023-09-29 14:14   ` Conor Dooley
2023-09-29 14:14     ` Conor Dooley
2023-09-29 14:45     ` Lad, Prabhakar
2023-09-29 14:45       ` Lad, Prabhakar
2023-10-03 12:34   ` Geert Uytterhoeven
2023-10-03 12:34     ` Geert Uytterhoeven
2023-10-27 22:11     ` Palmer Dabbelt
2023-10-27 22:11       ` Palmer Dabbelt
2023-10-28 21:27       ` Samuel Holland
2023-10-28 21:27         ` Samuel Holland
2023-10-29  8:00         ` Geert Uytterhoeven
2023-10-29  8:00           ` Geert Uytterhoeven
2023-11-02 20:20 ` [PATCH 0/5] Enable peripherals on RZ/Five SMARC EVK patchwork-bot+linux-riscv
2023-11-02 20:20   ` patchwork-bot+linux-riscv

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