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From: Jonathan Cavitt <jonathan.cavitt@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: andi.shyti@intel.com, jonathan.cavitt@intel.com,
	saurabhg.gupta@intel.com, nirmoy.das@intel.com
Subject: [Intel-gfx] [RFC PATCH 01/10] drm/i915: Add GuC TLB Invalidation device info flags
Date: Tue, 10 Oct 2023 11:44:12 -0700	[thread overview]
Message-ID: <20231010184423.2118908-2-jonathan.cavitt@intel.com> (raw)
In-Reply-To: <20231010184423.2118908-1-jonathan.cavitt@intel.com>

Add device info flags for if GuC TLB Invalidation is enabled.

Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 2 ++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb60fc9cf8737..6a2a78c61f212 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -794,6 +794,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_GUC_DEPRIVILEGE(i915) \
 	(INTEL_INFO(i915)->has_guc_deprivilege)
 
+#define HAS_GUC_TLB_INVALIDATION(i915)	(INTEL_INFO(i915)->has_guc_tlb_invalidation)
+
 #define HAS_3D_PIPELINE(i915)	(INTEL_INFO(i915)->has_3d_pipeline)
 
 #define HAS_ONE_EU_PER_FUSE_BIT(i915)	(INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 39817490b13fd..eba2f0b919c87 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -153,6 +153,7 @@ enum intel_ppgtt_type {
 	func(has_heci_pxp); \
 	func(has_heci_gscfi); \
 	func(has_guc_deprivilege); \
+	func(has_guc_tlb_invalidation); \
 	func(has_l3_ccs_read); \
 	func(has_l3_dpf); \
 	func(has_llc); \
-- 
2.25.1


  reply	other threads:[~2023-10-10 18:55 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-10 18:44 [Intel-gfx] [RFC PATCH 00/10] drm/i915: Implement range-based TLB Jonathan Cavitt
2023-10-10 18:44 ` Jonathan Cavitt [this message]
2023-10-10 18:44 ` [Intel-gfx] [PATCH dii-client 1/2] drm/i915: Add generic interface for tlb invalidation Jonathan Cavitt
2023-10-11  0:10   ` kernel test robot
2023-10-11  0:10     ` kernel test robot
2023-10-11  1:35   ` kernel test robot
2023-10-11  1:35     ` kernel test robot
2023-10-10 18:44 ` [Intel-gfx] [PATCH dii-client 2/2] drm/i915: Use selective tlb invalidations where supported Jonathan Cavitt
2023-10-10 19:37   ` Cavitt, Jonathan
2023-10-12  0:24   ` kernel test robot
2023-10-12  0:24     ` kernel test robot
2023-10-21 15:43   ` kernel test robot
2023-10-21 15:43     ` kernel test robot
2023-10-10 18:44 ` [Intel-gfx] [RFC PATCH 02/10] drm/i915/guc: Add CT size delay helper Jonathan Cavitt
2023-10-10 18:44 ` [Intel-gfx] [RFC PATCH 03/10] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-10 18:44 ` [Intel-gfx] [RFC PATCH 04/10] drm/i915: No TLB invalidation on suspended GT Jonathan Cavitt
2023-10-10 18:44 ` [Intel-gfx] [RFC PATCH 05/10] drm/i915: No TLB invalidation on wedged GT Jonathan Cavitt
2023-10-10 18:44 ` [Intel-gfx] [RFC PATCH 06/10] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck Jonathan Cavitt
2023-10-10 18:44 ` [Intel-gfx] [RFC PATCH 07/10] drm/i915: Enable GuC TLB invalidations for MTL Jonathan Cavitt
2023-10-10 18:44 ` [Intel-gfx] [RFC PATCH 08/10] drm/i915: Define GuC Based TLB invalidation routines Jonathan Cavitt
2023-10-10 18:44 ` [Intel-gfx] [RFC PATCH 09/10] drm/i915: Add generic interface for tlb invalidation Jonathan Cavitt
2023-10-10 18:44 ` [Intel-gfx] [RFC PATCH 10/10] drm/i915: Use selective tlb invalidations where supported Jonathan Cavitt
2023-10-11  8:16   ` Tvrtko Ursulin
2023-10-10 18:46 [Intel-gfx] [RFC PATCH 00/10] drm/i915: Implement range-based TLB Jonathan Cavitt
2023-10-10 18:46 ` [Intel-gfx] [RFC PATCH 01/10] drm/i915: Add GuC TLB Invalidation device info flags Jonathan Cavitt

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