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From: Linus Walleij <linus.walleij@linaro.org>
To: Aaro Koskinen <aaro.koskinen@iki.fi>,
	Janusz Krzysztofik <jmkrzyszt@gmail.com>,
	Tony Lindgren <tony@atomide.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Ben Dooks <ben.dooks@codethink.co.uk>
Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
	devicetree@vger.kernel.org, linux-mips@vger.kernel.org,
	Linus Walleij <linus.walleij@linaro.org>
Subject: [PATCH 3/6] MIPS: NI 169445: Fix NAND GPIOs
Date: Wed, 08 Nov 2023 15:33:51 +0100	[thread overview]
Message-ID: <20231108-fix-mips-nand-v1-3-5fc5586d04de@linaro.org> (raw)
In-Reply-To: <20231108-fix-mips-nand-v1-0-5fc5586d04de@linaro.org>

This changes the GPIOs defined in the device tree to recommended
practice, which is also what the Linux NAND GPIO driver is actually
using.

In the process, fix up the CE and WP lines to be active low, as is
required for proper hardware description.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/mips/boot/dts/ni/169445.dts | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/mips/boot/dts/ni/169445.dts b/arch/mips/boot/dts/ni/169445.dts
index 5389ef46c480..3e7b46d5072c 100644
--- a/arch/mips/boot/dts/ni/169445.dts
+++ b/arch/mips/boot/dts/ni/169445.dts
@@ -1,4 +1,5 @@
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	#address-cells = <1>;
@@ -57,18 +58,18 @@ gpio2: gpio@14 {
 			no-output;
 		};
 
-		nand@0 {
+		nand-controller@0 {
 			compatible = "gpio-control-nand";
 			nand-on-flash-bbt;
 			nand-ecc-mode = "soft_bch";
 			nand-ecc-step-size = <512>;
 			nand-ecc-strength = <4>;
 			reg = <0x0 4>;
-			gpios = <&gpio2 0 0>, /* rdy */
-				<&gpio1 1 0>, /* nce */
-				<&gpio1 2 0>, /* ale */
-				<&gpio1 3 0>, /* cle */
-				<&gpio1 4 0>; /* nwp */
+			rdy-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+			ce-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+			ale-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+			cle-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+			wp-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 		};
 
 		serial@80000 {

-- 
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: Linus Walleij <linus.walleij@linaro.org>
To: Aaro Koskinen <aaro.koskinen@iki.fi>,
	 Janusz Krzysztofik <jmkrzyszt@gmail.com>,
	Tony Lindgren <tony@atomide.com>,
	 Miquel Raynal <miquel.raynal@bootlin.com>,
	 Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	 Rob Herring <robh+dt@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	 Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	 Ben Dooks <ben.dooks@codethink.co.uk>
Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	 linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
	 devicetree@vger.kernel.org, linux-mips@vger.kernel.org,
	 Linus Walleij <linus.walleij@linaro.org>
Subject: [PATCH 3/6] MIPS: NI 169445: Fix NAND GPIOs
Date: Wed, 08 Nov 2023 15:33:51 +0100	[thread overview]
Message-ID: <20231108-fix-mips-nand-v1-3-5fc5586d04de@linaro.org> (raw)
In-Reply-To: <20231108-fix-mips-nand-v1-0-5fc5586d04de@linaro.org>

This changes the GPIOs defined in the device tree to recommended
practice, which is also what the Linux NAND GPIO driver is actually
using.

In the process, fix up the CE and WP lines to be active low, as is
required for proper hardware description.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/mips/boot/dts/ni/169445.dts | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/mips/boot/dts/ni/169445.dts b/arch/mips/boot/dts/ni/169445.dts
index 5389ef46c480..3e7b46d5072c 100644
--- a/arch/mips/boot/dts/ni/169445.dts
+++ b/arch/mips/boot/dts/ni/169445.dts
@@ -1,4 +1,5 @@
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	#address-cells = <1>;
@@ -57,18 +58,18 @@ gpio2: gpio@14 {
 			no-output;
 		};
 
-		nand@0 {
+		nand-controller@0 {
 			compatible = "gpio-control-nand";
 			nand-on-flash-bbt;
 			nand-ecc-mode = "soft_bch";
 			nand-ecc-step-size = <512>;
 			nand-ecc-strength = <4>;
 			reg = <0x0 4>;
-			gpios = <&gpio2 0 0>, /* rdy */
-				<&gpio1 1 0>, /* nce */
-				<&gpio1 2 0>, /* ale */
-				<&gpio1 3 0>, /* cle */
-				<&gpio1 4 0>; /* nwp */
+			rdy-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+			ce-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+			ale-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+			cle-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+			wp-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 		};
 
 		serial@80000 {

-- 
2.34.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Linus Walleij <linus.walleij@linaro.org>
To: Aaro Koskinen <aaro.koskinen@iki.fi>,
	 Janusz Krzysztofik <jmkrzyszt@gmail.com>,
	Tony Lindgren <tony@atomide.com>,
	 Miquel Raynal <miquel.raynal@bootlin.com>,
	 Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	 Rob Herring <robh+dt@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	 Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	 Ben Dooks <ben.dooks@codethink.co.uk>
Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	 linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
	 devicetree@vger.kernel.org, linux-mips@vger.kernel.org,
	 Linus Walleij <linus.walleij@linaro.org>
Subject: [PATCH 3/6] MIPS: NI 169445: Fix NAND GPIOs
Date: Wed, 08 Nov 2023 15:33:51 +0100	[thread overview]
Message-ID: <20231108-fix-mips-nand-v1-3-5fc5586d04de@linaro.org> (raw)
In-Reply-To: <20231108-fix-mips-nand-v1-0-5fc5586d04de@linaro.org>

This changes the GPIOs defined in the device tree to recommended
practice, which is also what the Linux NAND GPIO driver is actually
using.

In the process, fix up the CE and WP lines to be active low, as is
required for proper hardware description.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/mips/boot/dts/ni/169445.dts | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/mips/boot/dts/ni/169445.dts b/arch/mips/boot/dts/ni/169445.dts
index 5389ef46c480..3e7b46d5072c 100644
--- a/arch/mips/boot/dts/ni/169445.dts
+++ b/arch/mips/boot/dts/ni/169445.dts
@@ -1,4 +1,5 @@
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	#address-cells = <1>;
@@ -57,18 +58,18 @@ gpio2: gpio@14 {
 			no-output;
 		};
 
-		nand@0 {
+		nand-controller@0 {
 			compatible = "gpio-control-nand";
 			nand-on-flash-bbt;
 			nand-ecc-mode = "soft_bch";
 			nand-ecc-step-size = <512>;
 			nand-ecc-strength = <4>;
 			reg = <0x0 4>;
-			gpios = <&gpio2 0 0>, /* rdy */
-				<&gpio1 1 0>, /* nce */
-				<&gpio1 2 0>, /* ale */
-				<&gpio1 3 0>, /* cle */
-				<&gpio1 4 0>; /* nwp */
+			rdy-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+			ce-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+			ale-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+			cle-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+			wp-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 		};
 
 		serial@80000 {

-- 
2.34.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2023-11-08 14:34 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-08 14:33 [PATCH 0/6] Fix polarity and bindings for GPIO-based NAND drivers Linus Walleij
2023-11-08 14:33 ` Linus Walleij
2023-11-08 14:33 ` Linus Walleij
2023-11-08 14:33 ` [PATCH 1/6] mtd: rawnand: ams-delta/gpio: Unify polarity Linus Walleij
2023-11-08 14:33   ` Linus Walleij
2023-11-08 14:33   ` Linus Walleij
2023-11-08 14:33 ` [PATCH 2/6] dt-bindings: mtd: Rewrite gpio-control-nand in schema Linus Walleij
2023-11-08 14:33   ` Linus Walleij
2023-11-08 14:33   ` Linus Walleij
2023-11-08 16:22   ` Miquel Raynal
2023-11-08 16:22     ` Miquel Raynal
2023-11-08 16:22     ` Miquel Raynal
2023-11-08 19:11   ` Rob Herring
2023-11-08 19:11     ` Rob Herring
2023-11-08 19:11     ` Rob Herring
2023-11-08 21:45     ` Linus Walleij
2023-11-08 21:45       ` Linus Walleij
2023-11-08 21:45       ` Linus Walleij
2023-11-08 14:33 ` Linus Walleij [this message]
2023-11-08 14:33   ` [PATCH 3/6] MIPS: NI 169445: Fix NAND GPIOs Linus Walleij
2023-11-08 14:33   ` Linus Walleij
2023-11-08 14:33 ` [PATCH 4/6] mtd: rawnand: gpio: Use device properties Linus Walleij
2023-11-08 14:33   ` Linus Walleij
2023-11-08 14:33   ` Linus Walleij
2023-11-08 15:53   ` Miquel Raynal
2023-11-08 15:53     ` Miquel Raynal
2023-11-08 15:53     ` Miquel Raynal
2023-11-08 14:33 ` [PATCH 5/6] mtd: rawnand: gpio: Support standard nand width Linus Walleij
2023-11-08 14:33   ` Linus Walleij
2023-11-08 14:33   ` Linus Walleij
2023-11-08 15:56   ` Miquel Raynal
2023-11-08 15:56     ` Miquel Raynal
2023-11-08 15:56     ` Miquel Raynal
2023-11-08 14:33 ` [PATCH 6/6] mtd: rawnand: gpio: Rename file Linus Walleij
2023-11-08 14:33   ` Linus Walleij
2023-11-08 14:33   ` Linus Walleij
2023-11-08 15:59   ` Miquel Raynal
2023-11-08 15:59     ` Miquel Raynal
2023-11-08 15:59     ` Miquel Raynal

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