From: Imre Deak <imre.deak@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [PATCH v2 03/11] drm/dp_mst: Add kunit tests for drm_dp_get_vc_payload_bw() Date: Thu, 16 Nov 2023 15:18:33 +0200 [thread overview] Message-ID: <20231116131841.1588781-4-imre.deak@intel.com> (raw) In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> Add kunit test cases for drm_dp_get_vc_payload_bw() with all the DP1.4 and UHBR link configurations. Cc: Lyude Paul <lyude@redhat.com> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak <imre.deak@intel.com> --- .../gpu/drm/tests/drm_dp_mst_helper_test.c | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c index e3c818dfc0e6d..cafb463124f71 100644 --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c @@ -68,6 +68,150 @@ static void dp_mst_calc_pbn_mode_desc(const struct drm_dp_mst_calc_pbn_mode_test KUNIT_ARRAY_PARAM(drm_dp_mst_calc_pbn_mode, drm_dp_mst_calc_pbn_mode_cases, dp_mst_calc_pbn_mode_desc); +struct drm_dp_mst_calc_pbn_div_test { + int link_rate; + int lane_count; + fixed20_12 expected; +}; + +#define fp_init(__int, __frac) { \ + .full = (__int) * (1 << 12) + \ + (__frac) * (1 << 12) / 100000 \ +} + +static const struct drm_dp_mst_calc_pbn_div_test drm_dp_mst_calc_pbn_div_dp1_4_cases[] = { + /* + * DP1.4 rates: + * .expected = .link_rate * .lane_count * 0.8000 / 8 / 54 / 100 + * UHBR rates: + * .expected = .link_rate * .lane_count * 0.9671 / 8 / 54 / 100 + * truncated to 5 decimal places. + */ + { + .link_rate = 162000, + .lane_count = 1, + .expected = fp_init(3, 0), + }, + { + .link_rate = 162000, + .lane_count = 2, + .expected = fp_init(6, 0), + }, + { + .link_rate = 162000, + .lane_count = 4, + .expected = fp_init(12, 0), + }, + { + .link_rate = 270000, + .lane_count = 1, + .expected = fp_init(5, 0), + }, + { + .link_rate = 270000, + .lane_count = 2, + .expected = fp_init(10, 0), + }, + { + .link_rate = 270000, + .lane_count = 4, + .expected = fp_init(20, 0), + }, + { + .link_rate = 540000, + .lane_count = 1, + .expected = fp_init(10, 0), + }, + { + .link_rate = 540000, + .lane_count = 2, + .expected = fp_init(20, 0), + }, + { + .link_rate = 540000, + .lane_count = 4, + .expected = fp_init(40, 0), + }, + { + .link_rate = 810000, + .lane_count = 1, + .expected = fp_init(15, 0), + }, + { + .link_rate = 810000, + .lane_count = 2, + .expected = fp_init(30, 0), + }, + { + .link_rate = 810000, + .lane_count = 4, + .expected = fp_init(60, 0), + }, + { + .link_rate = 1000000, + .lane_count = 1, + .expected = fp_init(22, 38657), + }, + { + .link_rate = 1000000, + .lane_count = 2, + .expected = fp_init(44, 77314), + }, + { + .link_rate = 1000000, + .lane_count = 4, + .expected = fp_init(89, 54629), + }, + { + .link_rate = 1350000, + .lane_count = 1, + .expected = fp_init(30, 22187), + }, + { + .link_rate = 1350000, + .lane_count = 2, + .expected = fp_init(60, 44375), + }, + { + .link_rate = 1350000, + .lane_count = 4, + .expected = fp_init(120, 88750), + }, + { + .link_rate = 2000000, + .lane_count = 1, + .expected = fp_init(44, 77314), + }, + { + .link_rate = 2000000, + .lane_count = 2, + .expected = fp_init(89, 54629), + }, + { + .link_rate = 2000000, + .lane_count = 4, + .expected = fp_init(179, 9259), /* 179.09259 */ + }, +}; + +static void drm_test_dp_mst_calc_pbn_div(struct kunit *test) +{ + const struct drm_dp_mst_calc_pbn_div_test *params = test->param_value; + /* mgr->dev is only needed by drm_dbg_kms(), but it's not called for the test cases. */ + struct drm_dp_mst_topology_mgr mgr = {}; + + KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(&mgr, params->link_rate, params->lane_count).full, + params->expected.full); +} + +static void dp_mst_calc_pbn_div_desc(const struct drm_dp_mst_calc_pbn_div_test *t, char *desc) +{ + sprintf(desc, "Link rate %d lane count %d", t->link_rate, t->lane_count); +} + +KUNIT_ARRAY_PARAM(drm_dp_mst_calc_pbn_div, drm_dp_mst_calc_pbn_div_dp1_4_cases, + dp_mst_calc_pbn_div_desc); + static u8 data[] = { 0xff, 0x00, 0xdd }; struct drm_dp_mst_sideband_msg_req_test { @@ -416,6 +560,7 @@ KUNIT_ARRAY_PARAM(drm_dp_mst_sideband_msg_req, drm_dp_mst_sideband_msg_req_cases static struct kunit_case drm_dp_mst_helper_tests[] = { KUNIT_CASE_PARAM(drm_test_dp_mst_calc_pbn_mode, drm_dp_mst_calc_pbn_mode_gen_params), + KUNIT_CASE_PARAM(drm_test_dp_mst_calc_pbn_div, drm_dp_mst_calc_pbn_div_gen_params), KUNIT_CASE_PARAM(drm_test_dp_mst_sideband_msg_req_decode, drm_dp_mst_sideband_msg_req_gen_params), { } -- 2.39.2
WARNING: multiple messages have this Message-ID (diff)
From: Imre Deak <imre.deak@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2 03/11] drm/dp_mst: Add kunit tests for drm_dp_get_vc_payload_bw() Date: Thu, 16 Nov 2023 15:18:33 +0200 [thread overview] Message-ID: <20231116131841.1588781-4-imre.deak@intel.com> (raw) In-Reply-To: <20231116131841.1588781-1-imre.deak@intel.com> Add kunit test cases for drm_dp_get_vc_payload_bw() with all the DP1.4 and UHBR link configurations. Cc: Lyude Paul <lyude@redhat.com> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak <imre.deak@intel.com> --- .../gpu/drm/tests/drm_dp_mst_helper_test.c | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c index e3c818dfc0e6d..cafb463124f71 100644 --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c @@ -68,6 +68,150 @@ static void dp_mst_calc_pbn_mode_desc(const struct drm_dp_mst_calc_pbn_mode_test KUNIT_ARRAY_PARAM(drm_dp_mst_calc_pbn_mode, drm_dp_mst_calc_pbn_mode_cases, dp_mst_calc_pbn_mode_desc); +struct drm_dp_mst_calc_pbn_div_test { + int link_rate; + int lane_count; + fixed20_12 expected; +}; + +#define fp_init(__int, __frac) { \ + .full = (__int) * (1 << 12) + \ + (__frac) * (1 << 12) / 100000 \ +} + +static const struct drm_dp_mst_calc_pbn_div_test drm_dp_mst_calc_pbn_div_dp1_4_cases[] = { + /* + * DP1.4 rates: + * .expected = .link_rate * .lane_count * 0.8000 / 8 / 54 / 100 + * UHBR rates: + * .expected = .link_rate * .lane_count * 0.9671 / 8 / 54 / 100 + * truncated to 5 decimal places. + */ + { + .link_rate = 162000, + .lane_count = 1, + .expected = fp_init(3, 0), + }, + { + .link_rate = 162000, + .lane_count = 2, + .expected = fp_init(6, 0), + }, + { + .link_rate = 162000, + .lane_count = 4, + .expected = fp_init(12, 0), + }, + { + .link_rate = 270000, + .lane_count = 1, + .expected = fp_init(5, 0), + }, + { + .link_rate = 270000, + .lane_count = 2, + .expected = fp_init(10, 0), + }, + { + .link_rate = 270000, + .lane_count = 4, + .expected = fp_init(20, 0), + }, + { + .link_rate = 540000, + .lane_count = 1, + .expected = fp_init(10, 0), + }, + { + .link_rate = 540000, + .lane_count = 2, + .expected = fp_init(20, 0), + }, + { + .link_rate = 540000, + .lane_count = 4, + .expected = fp_init(40, 0), + }, + { + .link_rate = 810000, + .lane_count = 1, + .expected = fp_init(15, 0), + }, + { + .link_rate = 810000, + .lane_count = 2, + .expected = fp_init(30, 0), + }, + { + .link_rate = 810000, + .lane_count = 4, + .expected = fp_init(60, 0), + }, + { + .link_rate = 1000000, + .lane_count = 1, + .expected = fp_init(22, 38657), + }, + { + .link_rate = 1000000, + .lane_count = 2, + .expected = fp_init(44, 77314), + }, + { + .link_rate = 1000000, + .lane_count = 4, + .expected = fp_init(89, 54629), + }, + { + .link_rate = 1350000, + .lane_count = 1, + .expected = fp_init(30, 22187), + }, + { + .link_rate = 1350000, + .lane_count = 2, + .expected = fp_init(60, 44375), + }, + { + .link_rate = 1350000, + .lane_count = 4, + .expected = fp_init(120, 88750), + }, + { + .link_rate = 2000000, + .lane_count = 1, + .expected = fp_init(44, 77314), + }, + { + .link_rate = 2000000, + .lane_count = 2, + .expected = fp_init(89, 54629), + }, + { + .link_rate = 2000000, + .lane_count = 4, + .expected = fp_init(179, 9259), /* 179.09259 */ + }, +}; + +static void drm_test_dp_mst_calc_pbn_div(struct kunit *test) +{ + const struct drm_dp_mst_calc_pbn_div_test *params = test->param_value; + /* mgr->dev is only needed by drm_dbg_kms(), but it's not called for the test cases. */ + struct drm_dp_mst_topology_mgr mgr = {}; + + KUNIT_EXPECT_EQ(test, drm_dp_get_vc_payload_bw(&mgr, params->link_rate, params->lane_count).full, + params->expected.full); +} + +static void dp_mst_calc_pbn_div_desc(const struct drm_dp_mst_calc_pbn_div_test *t, char *desc) +{ + sprintf(desc, "Link rate %d lane count %d", t->link_rate, t->lane_count); +} + +KUNIT_ARRAY_PARAM(drm_dp_mst_calc_pbn_div, drm_dp_mst_calc_pbn_div_dp1_4_cases, + dp_mst_calc_pbn_div_desc); + static u8 data[] = { 0xff, 0x00, 0xdd }; struct drm_dp_mst_sideband_msg_req_test { @@ -416,6 +560,7 @@ KUNIT_ARRAY_PARAM(drm_dp_mst_sideband_msg_req, drm_dp_mst_sideband_msg_req_cases static struct kunit_case drm_dp_mst_helper_tests[] = { KUNIT_CASE_PARAM(drm_test_dp_mst_calc_pbn_mode, drm_dp_mst_calc_pbn_mode_gen_params), + KUNIT_CASE_PARAM(drm_test_dp_mst_calc_pbn_div, drm_dp_mst_calc_pbn_div_gen_params), KUNIT_CASE_PARAM(drm_test_dp_mst_sideband_msg_req_decode, drm_dp_mst_sideband_msg_req_gen_params), { } -- 2.39.2
next prev parent reply other threads:[~2023-11-16 13:19 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-11-16 13:18 [Intel-gfx] [PATCH v2 00/11] drm/i915: Fix UHBR data, link M/N/TU and PBN values Imre Deak 2023-11-16 13:18 ` [PATCH v2 01/11] drm/dp_mst: Store the MST PBN divider value in fixed point format Imre Deak 2023-11-16 13:18 ` Imre Deak 2023-11-16 13:18 ` [Intel-gfx] " Imre Deak 2023-11-17 10:56 ` Ville Syrjälä 2023-11-17 10:56 ` [Intel-gfx] " Ville Syrjälä 2023-11-17 14:11 ` Imre Deak 2023-11-17 14:11 ` [Intel-gfx] " Imre Deak 2023-11-21 13:54 ` Imre Deak 2023-11-21 13:54 ` Imre Deak 2023-11-16 13:18 ` [PATCH v2 02/11] drm/dp_mst: Fix PBN divider calculation for UHBR rates Imre Deak 2023-11-16 13:18 ` [Intel-gfx] " Imre Deak 2023-11-17 11:00 ` Ville Syrjälä 2023-11-17 13:58 ` Imre Deak 2023-11-17 15:09 ` [Intel-gfx] [PATCH v3 " Imre Deak 2023-11-17 15:09 ` Imre Deak 2023-11-17 16:21 ` Ville Syrjälä 2023-11-17 16:21 ` [Intel-gfx] " Ville Syrjälä 2023-11-17 19:40 ` Rodrigo Vivi 2023-11-21 13:39 ` Maarten Lankhorst 2023-11-16 13:18 ` Imre Deak [this message] 2023-11-16 13:18 ` [Intel-gfx] [PATCH v2 03/11] drm/dp_mst: Add kunit tests for drm_dp_get_vc_payload_bw() Imre Deak 2023-11-17 11:04 ` Ville Syrjälä 2023-11-17 14:35 ` Imre Deak 2023-11-17 15:09 ` [Intel-gfx] [PATCH v3 " Imre Deak 2023-11-17 15:09 ` Imre Deak 2023-11-17 15:27 ` [PATCH v4 " Imre Deak 2023-11-17 15:27 ` [Intel-gfx] " Imre Deak 2023-11-17 16:18 ` Ville Syrjälä 2023-11-17 16:18 ` [Intel-gfx] " Ville Syrjälä 2023-11-20 12:52 ` [PATCH v5 " Imre Deak 2023-11-20 12:52 ` [Intel-gfx] " Imre Deak 2023-11-18 23:41 ` [Intel-gfx] [PATCH v2 " kernel test robot 2023-11-18 23:41 ` kernel test robot 2023-11-16 13:18 ` [Intel-gfx] [PATCH v2 04/11] drm/i915/dp: Replace intel_dp_is_uhbr_rate() with drm_dp_is_uhbr_rate() Imre Deak 2023-11-17 3:21 ` Murthy, Arun R 2023-11-16 13:18 ` [Intel-gfx] [PATCH v2 05/11] drm/i915/dp: Account for channel coding efficiency on UHBR links Imre Deak 2023-11-16 13:18 ` [Intel-gfx] [PATCH v2 06/11] drm/i915/dp: Fix UHBR link M/N values Imre Deak 2023-11-16 13:18 ` [Intel-gfx] [PATCH v2 07/11] drm/i915/dp_mst: Calculate the BW overhead in intel_dp_mst_find_vcpi_slots_for_bpp() Imre Deak 2023-11-17 9:18 ` Murthy, Arun R 2023-11-16 13:18 ` [Intel-gfx] [PATCH v2 08/11] drm/i915/dp_mst: Fix PBN / MTP_TU size calculation for UHBR rates Imre Deak 2023-11-17 15:09 ` [Intel-gfx] [PATCH v3 " Imre Deak 2023-11-16 13:18 ` [Intel-gfx] [PATCH v2 09/11] drm/i915/dp: Report a rounded-down value as the maximum data rate Imre Deak 2023-11-17 11:43 ` Lisovskiy, Stanislav 2023-11-16 13:18 ` [Intel-gfx] [PATCH v2 10/11] drm/i915/dp: Simplify intel_dp_max_data_rate() Imre Deak 2023-11-17 17:10 ` Ville Syrjälä 2023-11-16 13:18 ` [Intel-gfx] [PATCH v2 11/11] drm/i915/dp: Reuse intel_dp_{max, effective}_data_rate in intel_link_compute_m_n() Imre Deak 2023-11-17 17:11 ` Ville Syrjälä 2023-11-16 16:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix UHBR data, link M/N/TU and PBN values Patchwork 2023-11-16 16:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2023-11-16 17:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-11-17 14:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2023-11-17 20:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix UHBR data, link M/N/TU and PBN values (rev5) Patchwork 2023-11-17 20:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2023-11-17 20:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-11-18 17:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2023-11-20 12:31 ` [PATCH v2 00/11] drm/i915: Fix UHBR data,link M/N/TU and PBN values Jani Nikula 2023-11-20 12:31 ` [Intel-gfx] [PATCH v2 00/11] drm/i915: Fix UHBR data, link " Jani Nikula 2023-11-20 13:10 ` [PATCH v2 00/11] drm/i915: Fix UHBR data,link " Imre Deak 2023-11-20 13:10 ` [Intel-gfx] [PATCH v2 00/11] drm/i915: Fix UHBR data, link " Imre Deak 2023-11-20 13:36 ` [PATCH v2 00/11] drm/i915: Fix UHBR data,link " Jani Nikula 2023-11-20 13:36 ` [Intel-gfx] [PATCH v2 00/11] drm/i915: Fix UHBR data, link " Jani Nikula 2023-11-21 2:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix UHBR data, link M/N/TU and PBN values (rev6) Patchwork 2023-11-21 2:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2023-11-21 2:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2023-11-21 20:54 ` Imre Deak 2023-11-21 20:54 ` [Intel-gfx] " Imre Deak 2023-11-21 22:42 ` [Intel-gfx] [PATCH v2 00/11] drm/i915: Fix UHBR data, link M/N/TU and PBN values Lyude Paul
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