All of lore.kernel.org
 help / color / mirror / Atom feed
From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <acme@kernel.org>, <adrian.hunter@intel.com>,
	<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
	<andre.przywara@arm.com>, <anup@brainfault.org>,
	<aou@eecs.berkeley.edu>, <atishp@atishpatra.org>,
	<conor+dt@kernel.org>, <conor.dooley@microchip.com>,
	<conor@kernel.org>, <devicetree@vger.kernel.org>,
	<dminus@andestech.com>, <evan@rivosinc.com>,
	<geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>,
	<irogers@google.com>, <jernej.skrabec@gmail.com>,
	<jolsa@kernel.org>, <jszhang@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>,
	<linux-renesas-soc@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>,
	<locus84@andestech.com>, <magnus.damm@gmail.com>,
	<mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>,
	<namhyung@kernel.org>, <palmer@dabbelt.com>,
	<paul.walmsley@sifive.com>, <peterlin@andestech.com>,
	<peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<rdunlap@infradead.org>, <robh+dt@kernel.org>,
	<samuel@sholland.org>, <sunilvl@ventanamicro.com>,
	<tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>,
	<wens@csie.org>, <will@kernel.org>, <ycliang@andestech.com>,
	<inochiama@outlook.com>
Subject: [PATCH v4 06/13] perf: RISC-V: Eliminate redundant interrupt enable/disable operations
Date: Wed, 22 Nov 2023 20:12:28 +0800	[thread overview]
Message-ID: <20231122121235.827122-7-peterlin@andestech.com> (raw)
In-Reply-To: <20231122121235.827122-1-peterlin@andestech.com>

The interrupt enable/disable operations are already performed by the
IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during
enable_percpu_irq()/disable_percpu_irq(). We can just do it once.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
This patch allows us to drop unnecessary ALT_SBI_PMU_OVF_{DISABLE,ENABLE}
in the last PATCH3 [1].

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20230907021635.1002738-4-peterlin@andestech.com/

Changes v1 -> v2:
  - New patch
Changes v2 -> v3:
  - No change
Changes v3 -> v4:
  - No change
---
 drivers/perf/riscv_pmu_sbi.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 16acd4dcdb96..2edbc37abadf 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
 	if (riscv_pmu_use_irq) {
 		cpu_hw_evt->irq = riscv_pmu_irq;
 		csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
-		csr_set(CSR_IE, BIT(riscv_pmu_irq_num));
 		enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
 	}
 
@@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
 {
 	if (riscv_pmu_use_irq) {
 		disable_percpu_irq(riscv_pmu_irq);
-		csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));
 	}
 
 	/* Disable all counters access for user mode now */
-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <acme@kernel.org>, <adrian.hunter@intel.com>,
	<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
	<andre.przywara@arm.com>, <anup@brainfault.org>,
	<aou@eecs.berkeley.edu>, <atishp@atishpatra.org>,
	<conor+dt@kernel.org>, <conor.dooley@microchip.com>,
	<conor@kernel.org>, <devicetree@vger.kernel.org>,
	<dminus@andestech.com>, <evan@rivosinc.com>,
	<geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>,
	<irogers@google.com>, <jernej.skrabec@gmail.com>,
	<jolsa@kernel.org>, <jszhang@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>,
	<linux-renesas-soc@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>,
	<locus84@andestech.com>, <magnus.damm@gmail.com>,
	<mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>,
	<namhyung@kernel.org>, <palmer@dabbelt.com>,
	<paul.walmsley@sifive.com>, <peterlin@andestech.com>,
	<peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<rdunlap@infradead.org>, <robh+dt@kernel.org>,
	<samuel@sholland.org>, <sunilvl@ventanamicro.com>,
	<tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>,
	<wens@csie.org>, <will@kernel.org>, <ycliang@andestech.com>,
	<inochiama@outlook.com>
Subject: [PATCH v4 06/13] perf: RISC-V: Eliminate redundant interrupt enable/disable operations
Date: Wed, 22 Nov 2023 20:12:28 +0800	[thread overview]
Message-ID: <20231122121235.827122-7-peterlin@andestech.com> (raw)
In-Reply-To: <20231122121235.827122-1-peterlin@andestech.com>

The interrupt enable/disable operations are already performed by the
IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during
enable_percpu_irq()/disable_percpu_irq(). We can just do it once.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
This patch allows us to drop unnecessary ALT_SBI_PMU_OVF_{DISABLE,ENABLE}
in the last PATCH3 [1].

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20230907021635.1002738-4-peterlin@andestech.com/

Changes v1 -> v2:
  - New patch
Changes v2 -> v3:
  - No change
Changes v3 -> v4:
  - No change
---
 drivers/perf/riscv_pmu_sbi.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 16acd4dcdb96..2edbc37abadf 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
 	if (riscv_pmu_use_irq) {
 		cpu_hw_evt->irq = riscv_pmu_irq;
 		csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
-		csr_set(CSR_IE, BIT(riscv_pmu_irq_num));
 		enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
 	}
 
@@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
 {
 	if (riscv_pmu_use_irq) {
 		disable_percpu_irq(riscv_pmu_irq);
-		csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));
 	}
 
 	/* Disable all counters access for user mode now */
-- 
2.34.1


  parent reply	other threads:[~2023-11-22 12:17 UTC|newest]

Thread overview: 117+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-22 12:12 [PATCH v4 00/13] Support Andes PMU extension Yu Chien Peter Lin
2023-11-22 12:12 ` Yu Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 01/13] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-24 14:57   ` Lad, Prabhakar
2023-11-24 14:57     ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-12-08 15:54   ` Thomas Gleixner
2023-12-08 15:54     ` Thomas Gleixner
2023-12-12 10:17     ` Yu-Chien Peter Lin
2023-12-12 10:17       ` Yu-Chien Peter Lin
2023-12-12 10:17       ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 03/13] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-12-08 16:01   ` Thomas Gleixner
2023-12-08 16:01     ` Thomas Gleixner
2023-12-12 10:28     ` Yu-Chien Peter Lin
2023-12-12 10:28       ` Yu-Chien Peter Lin
2023-12-12 10:28       ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-23 14:38   ` Conor Dooley
2023-11-23 14:38     ` Conor Dooley
2023-11-23 14:38     ` Conor Dooley
2023-11-24 15:03   ` Lad, Prabhakar
2023-11-24 15:03     ` Lad, Prabhakar
2023-11-24 15:05     ` Conor Dooley
2023-11-24 15:05       ` Conor Dooley
2023-11-29  6:43     ` Yu-Chien Peter Lin
2023-11-29  6:43       ` Yu-Chien Peter Lin
2023-11-29  6:43       ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-22 16:36   ` Geert Uytterhoeven
2023-11-22 16:36     ` Geert Uytterhoeven
2023-11-22 16:36     ` Geert Uytterhoeven
2023-11-24 15:04   ` Lad, Prabhakar
2023-11-24 15:04     ` Lad, Prabhakar
2023-11-22 12:12 ` Yu Chien Peter Lin [this message]
2023-11-22 12:12   ` [PATCH v4 06/13] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-22 21:16   ` Guo Ren
2023-11-22 21:16     ` Guo Ren
2023-11-22 21:16     ` Guo Ren
2023-11-23 14:45   ` Conor Dooley
2023-11-23 14:45     ` Conor Dooley
2023-11-23 14:45     ` Conor Dooley
2023-11-22 12:12 ` [PATCH v4 08/13] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-24 15:06   ` Lad, Prabhakar
2023-11-24 15:06     ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-22 21:14   ` Guo Ren
2023-11-22 21:14     ` Guo Ren
2023-11-22 21:14     ` Guo Ren
2023-11-29  8:48     ` Yu-Chien Peter Lin
2023-11-29  8:48       ` Yu-Chien Peter Lin
2023-11-29  8:48       ` Yu-Chien Peter Lin
2023-11-30  8:29       ` Inochi Amaoto
2023-11-30  8:29         ` Inochi Amaoto
2023-11-30  9:21         ` Yu-Chien Peter Lin
2023-11-30  9:21           ` Yu-Chien Peter Lin
2023-11-30  9:21           ` Yu-Chien Peter Lin
2023-11-30 12:16           ` Inochi Amaoto
2023-11-30 12:16             ` Inochi Amaoto
2023-11-30 12:58             ` Conor Dooley
2023-11-30 12:58               ` Conor Dooley
2023-11-30 12:58               ` Conor Dooley
2023-11-30 23:11               ` Inochi Amaoto
2023-11-30 23:11                 ` Inochi Amaoto
2023-12-01  0:40                 ` Conor Dooley
2023-12-01  0:40                   ` Conor Dooley
2023-12-01  0:40                   ` Conor Dooley
2023-12-01  0:57                   ` Inochi Amaoto
2023-12-01  0:57                     ` Inochi Amaoto
2023-12-01  1:14           ` Inochi Amaoto
2023-12-01  1:14             ` Inochi Amaoto
2023-12-06  3:14             ` Yu-Chien Peter Lin
2023-12-06  3:14               ` Yu-Chien Peter Lin
2023-12-06  3:14               ` Yu-Chien Peter Lin
2023-11-23 14:48   ` Conor Dooley
2023-11-23 14:48     ` Conor Dooley
2023-11-23 14:48     ` Conor Dooley
2023-11-29  8:47     ` Yu-Chien Peter Lin
2023-11-29  8:47       ` Yu-Chien Peter Lin
2023-11-29  8:47       ` Yu-Chien Peter Lin
2023-11-29 12:33       ` Conor Dooley
2023-11-29 12:33         ` Conor Dooley
2023-11-29 12:33         ` Conor Dooley
2023-11-22 12:12 ` [PATCH v4 10/13] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-24 15:07   ` Lad, Prabhakar
2023-11-24 15:07     ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 11/13] riscv: dts: allwinner: Add T-Head PMU extension Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-22 21:12   ` Guo Ren
2023-11-22 21:12     ` Guo Ren
2023-11-22 21:12     ` Guo Ren
2023-11-23 14:58   ` Conor Dooley
2023-11-23 14:58     ` Conor Dooley
2023-11-23 14:58     ` Conor Dooley
2023-11-29  9:34     ` Yu-Chien Peter Lin
2023-11-29  9:34       ` Yu-Chien Peter Lin
2023-11-29  9:34       ` Yu-Chien Peter Lin
2023-11-22 12:12 ` [PATCH v4 12/13] riscv: dts: renesas: Add Andes " Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-22 16:34   ` Geert Uytterhoeven
2023-11-22 16:34     ` Geert Uytterhoeven
2023-11-24 15:07   ` Lad, Prabhakar
2023-11-24 15:07     ` Lad, Prabhakar
2023-11-22 12:12 ` [PATCH v4 13/13] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin
2023-11-22 12:12   ` Yu Chien Peter Lin
2023-11-24 15:08   ` Lad, Prabhakar
2023-11-24 15:08     ` Lad, Prabhakar

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20231122121235.827122-7-peterlin@andestech.com \
    --to=peterlin@andestech.com \
    --cc=acme@kernel.org \
    --cc=adrian.hunter@intel.com \
    --cc=ajones@ventanamicro.com \
    --cc=alexander.shishkin@linux.intel.com \
    --cc=andre.przywara@arm.com \
    --cc=anup@brainfault.org \
    --cc=aou@eecs.berkeley.edu \
    --cc=atishp@atishpatra.org \
    --cc=conor+dt@kernel.org \
    --cc=conor.dooley@microchip.com \
    --cc=conor@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=dminus@andestech.com \
    --cc=evan@rivosinc.com \
    --cc=geert+renesas@glider.be \
    --cc=guoren@kernel.org \
    --cc=heiko@sntech.de \
    --cc=inochiama@outlook.com \
    --cc=irogers@google.com \
    --cc=jernej.skrabec@gmail.com \
    --cc=jolsa@kernel.org \
    --cc=jszhang@kernel.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-perf-users@vger.kernel.org \
    --cc=linux-renesas-soc@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=linux-sunxi@lists.linux.dev \
    --cc=locus84@andestech.com \
    --cc=magnus.damm@gmail.com \
    --cc=mark.rutland@arm.com \
    --cc=mingo@redhat.com \
    --cc=n.shubin@yadro.com \
    --cc=namhyung@kernel.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=peterz@infradead.org \
    --cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
    --cc=rdunlap@infradead.org \
    --cc=robh+dt@kernel.org \
    --cc=samuel@sholland.org \
    --cc=sunilvl@ventanamicro.com \
    --cc=tglx@linutronix.de \
    --cc=tim609@andestech.com \
    --cc=uwu@icenowy.me \
    --cc=wens@csie.org \
    --cc=will@kernel.org \
    --cc=ycliang@andestech.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.