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From: Joey Gouly <joey.gouly@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: akpm@linux-foundation.org, aneesh.kumar@linux.ibm.com,
	broonie@kernel.org, catalin.marinas@arm.com,
	dave.hansen@linux.intel.com, joey.gouly@arm.com, maz@kernel.org,
	oliver.upton@linux.dev, shuah@kernel.org, will@kernel.org,
	kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org,
	linux-mm@kvack.org, linux-kselftest@vger.kernel.org,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v3 07/25] arm64: enable the Permission Overlay Extension for EL0
Date: Fri, 24 Nov 2023 16:34:52 +0000	[thread overview]
Message-ID: <20231124163510.1835740-8-joey.gouly@arm.com> (raw)
In-Reply-To: <20231124163510.1835740-1-joey.gouly@arm.com>

Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to
check if the CPU supports the feature.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 Documentation/arch/arm64/elf_hwcaps.rst |  3 +++
 arch/arm64/include/asm/hwcap.h          |  1 +
 arch/arm64/include/uapi/asm/hwcap.h     |  1 +
 arch/arm64/kernel/cpufeature.c          | 14 ++++++++++++++
 arch/arm64/kernel/cpuinfo.c             |  1 +
 5 files changed, 20 insertions(+)

diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst
index ced7b335e2e0..fe7350a66cea 100644
--- a/Documentation/arch/arm64/elf_hwcaps.rst
+++ b/Documentation/arch/arm64/elf_hwcaps.rst
@@ -317,6 +317,9 @@ HWCAP2_LRCPC3
 HWCAP2_LSE128
     Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011.
 
+HWCAP2_POE
+    Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001.
+
 4. Unused AT_HWCAP bits
 -----------------------
 
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index cd71e09ea14d..9a1aa1e5e25c 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -142,6 +142,7 @@
 #define KERNEL_HWCAP_SVE_B16B16		__khwcap2_feature(SVE_B16B16)
 #define KERNEL_HWCAP_LRCPC3		__khwcap2_feature(LRCPC3)
 #define KERNEL_HWCAP_LSE128		__khwcap2_feature(LSE128)
+#define KERNEL_HWCAP_POE		__khwcap2_feature(POE)
 
 /*
  * This yields a mask that user programs can use to figure out what
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
index 5023599fa278..69f09521b553 100644
--- a/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@ -107,5 +107,6 @@
 #define HWCAP2_SVE_B16B16	(1UL << 45)
 #define HWCAP2_LRCPC3		(1UL << 46)
 #define HWCAP2_LSE128		(1UL << 47)
+#define HWCAP2_POE		(1UL << 48)
 
 #endif /* _UAPI__ASM_HWCAP_H */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 00b6d516ed3f..02169cb3b84b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -402,6 +402,8 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {
+	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE),
+		       FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),
 	ARM64_FTR_END,
@@ -2242,6 +2244,14 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused)
 	sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);
 }
 
+#ifdef CONFIG_ARM64_POE
+static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused)
+{
+	sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE);
+	sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE);
+}
+#endif
+
 /* Internal helper functions to match cpu capability type */
 static bool
 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
@@ -2737,6 +2747,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.capability = ARM64_HAS_S1POE,
 		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
 		.matches = has_cpuid_feature,
+		.cpu_enable = cpu_enable_poe,
 		ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP)
 	},
 #endif
@@ -2889,6 +2900,9 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 	HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32),
 	HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
 #endif /* CONFIG_ARM64_SME */
+#ifdef CONFIG_ARM64_POE
+	HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE),
+#endif
 	{},
 };
 
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index a257da7b56fe..5515c50f5219 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -130,6 +130,7 @@ static const char *const hwcap_str[] = {
 	[KERNEL_HWCAP_SVE_B16B16]	= "sveb16b16",
 	[KERNEL_HWCAP_LRCPC3]		= "lrcpc3",
 	[KERNEL_HWCAP_LSE128]		= "lse128",
+	[KERNEL_HWCAP_POE]		= "poe",
 };
 
 #ifdef CONFIG_COMPAT
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Joey Gouly <joey.gouly@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: akpm@linux-foundation.org, aneesh.kumar@linux.ibm.com,
	broonie@kernel.org, catalin.marinas@arm.com,
	dave.hansen@linux.intel.com, joey.gouly@arm.com, maz@kernel.org,
	oliver.upton@linux.dev, shuah@kernel.org, will@kernel.org,
	kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org,
	linux-mm@kvack.org, linux-kselftest@vger.kernel.org,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v3 07/25] arm64: enable the Permission Overlay Extension for EL0
Date: Fri, 24 Nov 2023 16:34:52 +0000	[thread overview]
Message-ID: <20231124163510.1835740-8-joey.gouly@arm.com> (raw)
In-Reply-To: <20231124163510.1835740-1-joey.gouly@arm.com>

Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to
check if the CPU supports the feature.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 Documentation/arch/arm64/elf_hwcaps.rst |  3 +++
 arch/arm64/include/asm/hwcap.h          |  1 +
 arch/arm64/include/uapi/asm/hwcap.h     |  1 +
 arch/arm64/kernel/cpufeature.c          | 14 ++++++++++++++
 arch/arm64/kernel/cpuinfo.c             |  1 +
 5 files changed, 20 insertions(+)

diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst
index ced7b335e2e0..fe7350a66cea 100644
--- a/Documentation/arch/arm64/elf_hwcaps.rst
+++ b/Documentation/arch/arm64/elf_hwcaps.rst
@@ -317,6 +317,9 @@ HWCAP2_LRCPC3
 HWCAP2_LSE128
     Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011.
 
+HWCAP2_POE
+    Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001.
+
 4. Unused AT_HWCAP bits
 -----------------------
 
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index cd71e09ea14d..9a1aa1e5e25c 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -142,6 +142,7 @@
 #define KERNEL_HWCAP_SVE_B16B16		__khwcap2_feature(SVE_B16B16)
 #define KERNEL_HWCAP_LRCPC3		__khwcap2_feature(LRCPC3)
 #define KERNEL_HWCAP_LSE128		__khwcap2_feature(LSE128)
+#define KERNEL_HWCAP_POE		__khwcap2_feature(POE)
 
 /*
  * This yields a mask that user programs can use to figure out what
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
index 5023599fa278..69f09521b553 100644
--- a/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@ -107,5 +107,6 @@
 #define HWCAP2_SVE_B16B16	(1UL << 45)
 #define HWCAP2_LRCPC3		(1UL << 46)
 #define HWCAP2_LSE128		(1UL << 47)
+#define HWCAP2_POE		(1UL << 48)
 
 #endif /* _UAPI__ASM_HWCAP_H */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 00b6d516ed3f..02169cb3b84b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -402,6 +402,8 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {
+	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE),
+		       FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),
 	ARM64_FTR_END,
@@ -2242,6 +2244,14 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused)
 	sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);
 }
 
+#ifdef CONFIG_ARM64_POE
+static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused)
+{
+	sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE);
+	sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE);
+}
+#endif
+
 /* Internal helper functions to match cpu capability type */
 static bool
 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
@@ -2737,6 +2747,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.capability = ARM64_HAS_S1POE,
 		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
 		.matches = has_cpuid_feature,
+		.cpu_enable = cpu_enable_poe,
 		ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP)
 	},
 #endif
@@ -2889,6 +2900,9 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 	HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32),
 	HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
 #endif /* CONFIG_ARM64_SME */
+#ifdef CONFIG_ARM64_POE
+	HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE),
+#endif
 	{},
 };
 
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index a257da7b56fe..5515c50f5219 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -130,6 +130,7 @@ static const char *const hwcap_str[] = {
 	[KERNEL_HWCAP_SVE_B16B16]	= "sveb16b16",
 	[KERNEL_HWCAP_LRCPC3]		= "lrcpc3",
 	[KERNEL_HWCAP_LSE128]		= "lse128",
+	[KERNEL_HWCAP_POE]		= "poe",
 };
 
 #ifdef CONFIG_COMPAT
-- 
2.25.1


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2023-11-24 16:35 UTC|newest]

Thread overview: 122+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-24 16:34 [PATCH v3 00/25] Permission Overlay Extension Joey Gouly
2023-11-24 16:34 ` Joey Gouly
2023-11-24 16:34 ` [PATCH v3 01/25] arm64/sysreg: add system register POR_EL{0,1} Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-12-04 18:40   ` Catalin Marinas
2023-12-04 18:40     ` Catalin Marinas
2023-11-24 16:34 ` [PATCH v3 02/25] arm64/sysreg: update CPACR_EL1 register Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-12-04 18:41   ` Catalin Marinas
2023-12-04 18:41     ` Catalin Marinas
2023-11-24 16:34 ` [PATCH v3 03/25] arm64: cpufeature: add Permission Overlay Extension cpucap Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-11-25 12:11   ` Mark Brown
2023-11-25 12:11     ` Mark Brown
2023-12-04 18:46   ` Catalin Marinas
2023-12-04 18:46     ` Catalin Marinas
2023-11-24 16:34 ` [PATCH v3 04/25] arm64: disable trapping of POR_EL0 to EL2 Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-12-07 13:37   ` Catalin Marinas
2023-12-07 13:37     ` Catalin Marinas
2023-11-24 16:34 ` [PATCH v3 05/25] arm64: context switch POR_EL0 register Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-11-25 12:02   ` Mark Brown
2023-11-25 12:02     ` Mark Brown
2023-12-07 13:55     ` Catalin Marinas
2023-12-07 13:55       ` Catalin Marinas
2023-12-07 14:12       ` Mark Brown
2023-12-07 14:12         ` Mark Brown
2023-12-07 13:51   ` Catalin Marinas
2023-12-07 13:51     ` Catalin Marinas
2023-11-24 16:34 ` [PATCH v3 06/25] KVM: arm64: Save/restore POE registers Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-11-27 18:01   ` Marc Zyngier
2023-11-27 18:01     ` Marc Zyngier
2023-11-29 15:11     ` Joey Gouly
2023-11-29 15:11       ` Joey Gouly
2023-11-29 19:47       ` Marc Zyngier
2023-11-29 19:47         ` Marc Zyngier
2023-11-30 15:51   ` Marc Zyngier
2023-11-30 15:51     ` Marc Zyngier
2023-11-24 16:34 ` Joey Gouly [this message]
2023-11-24 16:34   ` [PATCH v3 07/25] arm64: enable the Permission Overlay Extension for EL0 Joey Gouly
2023-12-07 14:08   ` Catalin Marinas
2023-12-07 14:08     ` Catalin Marinas
2023-11-24 16:34 ` [PATCH v3 08/25] arm64: add POIndex defines Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-11-24 16:34 ` [PATCH v3 09/25] arm64: define VM_PKEY_BIT* for arm64 Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-12-07 15:10   ` Catalin Marinas
2023-12-07 15:10     ` Catalin Marinas
2023-11-24 16:34 ` [PATCH v3 10/25] arm64: mask out POIndex when modifying a PTE Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-12-07 15:11   ` Catalin Marinas
2023-12-07 15:11     ` Catalin Marinas
2023-11-24 16:34 ` [PATCH v3 11/25] arm64: enable ARCH_HAS_PKEYS on arm64 Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-12-07 15:25   ` Catalin Marinas
2023-12-07 15:25     ` Catalin Marinas
2023-12-07 15:44     ` Joey Gouly
2023-12-07 15:44       ` Joey Gouly
2023-11-24 16:34 ` [PATCH v3 12/25] arm64: handle PKEY/POE faults Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-12-11 18:18   ` Catalin Marinas
2023-12-11 18:18     ` Catalin Marinas
2023-12-13 15:02     ` Joey Gouly
2023-12-13 15:02       ` Joey Gouly
2023-11-24 16:34 ` [PATCH v3 13/25] arm64: stop using generic mm_hooks.h Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-12-11 18:22   ` Catalin Marinas
2023-12-11 18:22     ` Catalin Marinas
2023-11-24 16:34 ` [PATCH v3 14/25] arm64: implement PKEYS support Joey Gouly
2023-11-24 16:34   ` Joey Gouly
2023-12-11 18:49   ` Catalin Marinas
2023-12-11 18:49     ` Catalin Marinas
2023-12-14 13:47     ` Joey Gouly
2023-12-14 13:47       ` Joey Gouly
2023-11-24 16:35 ` [PATCH v3 15/25] arm64: add POE signal support Joey Gouly
2023-11-24 16:35   ` Joey Gouly
2023-12-11 18:53   ` Catalin Marinas
2023-12-11 18:53     ` Catalin Marinas
2023-12-12 12:03     ` Szabolcs Nagy
2023-12-12 12:03       ` Szabolcs Nagy
2023-11-24 16:35 ` [PATCH v3 16/25] arm64: enable PKEY support for CPUs with S1POE Joey Gouly
2023-11-24 16:35   ` Joey Gouly
2023-12-11 18:53   ` Catalin Marinas
2023-12-11 18:53     ` Catalin Marinas
2023-11-24 16:35 ` [PATCH v3 17/25] arm64: enable POE and PIE to coexist Joey Gouly
2023-11-24 16:35   ` Joey Gouly
2023-12-11 18:57   ` Catalin Marinas
2023-12-11 18:57     ` Catalin Marinas
2023-11-24 16:35 ` [PATCH v3 18/25] arm64/ptrace: add support for FEAT_POE Joey Gouly
2023-11-24 16:35   ` Joey Gouly
2023-11-24 17:18   ` Mark Brown
2023-11-24 17:18     ` Mark Brown
2023-12-11 18:58   ` Catalin Marinas
2023-12-11 18:58     ` Catalin Marinas
2023-11-24 16:35 ` [PATCH v3 19/25] kselftest/arm64: move get_header() Joey Gouly
2023-11-24 16:35   ` Joey Gouly
2023-11-24 17:16   ` Mark Brown
2023-11-24 17:16     ` Mark Brown
2023-11-24 16:35 ` [PATCH v3 20/25] selftests: mm: move fpregs printing Joey Gouly
2023-11-24 16:35   ` Joey Gouly
2023-11-24 16:35 ` [PATCH v3 21/25] selftests: mm: make protection_keys test work on arm64 Joey Gouly
2023-11-24 16:35   ` Joey Gouly
2023-11-24 16:35 ` [PATCH v3 22/25] kselftest/arm64: add HWCAP test for FEAT_S1POE Joey Gouly
2023-11-24 16:35   ` Joey Gouly
2023-11-24 17:02   ` Mark Brown
2023-11-24 17:02     ` Mark Brown
2023-11-24 16:35 ` [PATCH v3 23/25] kselftest/arm64: parse POE_MAGIC in a signal frame Joey Gouly
2023-11-24 16:35   ` Joey Gouly
2023-11-24 16:35 ` [PATCH v3 24/25] kselftest/arm64: Add test case for POR_EL0 signal frame records Joey Gouly
2023-11-24 16:35   ` Joey Gouly
2023-11-24 17:04   ` Mark Brown
2023-11-24 17:04     ` Mark Brown
2023-11-24 16:35 ` [PATCH v3 25/25] KVM: selftests: get-reg-list: add Permission Overlay registers Joey Gouly
2023-11-24 16:35   ` Joey Gouly
2023-11-24 17:07   ` Mark Brown
2023-11-24 17:07     ` Mark Brown
2023-12-04 11:03 ` [PATCH v3 00/25] Permission Overlay Extension Marc Zyngier
2023-12-04 11:03   ` Marc Zyngier
2023-12-05 15:41   ` Joey Gouly
2023-12-05 15:41     ` Joey Gouly

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