From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 10/12] clk: renesas: r9a07g044: Add GPT clock and reset entry
Date: Thu, 7 Dec 2023 10:55:06 +0000 [thread overview]
Message-ID: <20231207105508.171162-11-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20231207105508.171162-1-biju.das.jz@bp.renesas.com>
commit 1fb7a9fb6295220eb96c490581316b35fce180fe upstream.
Add GPT clock and reset entry to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220510110653.7326-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index ab546d57cb60..c61ff71b60eb 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -182,7 +182,7 @@ static const struct {
};
static const struct {
- struct rzg2l_mod_clk common[70];
+ struct rzg2l_mod_clk common[71];
#ifdef CONFIG_CLK_R9A07G054
struct rzg2l_mod_clk drp[0];
#endif
@@ -206,6 +206,8 @@ static const struct {
0x534, 2),
DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
0x538, 0),
+ DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
+ 0x540, 0),
DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
0x548, 0),
DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
@@ -345,6 +347,7 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
+ DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
--
2.25.1
next prev parent reply other threads:[~2023-12-07 10:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-07 10:54 [PATCH 5.10.y-cip 00/12] Add display/dsi/gpt/poeg clk support Biju Das
2023-12-07 10:54 ` [PATCH 5.10.y-cip 01/12] clk: renesas: rzg2l: Add FOUTPOSTDIV " Biju Das
2023-12-07 10:54 ` [PATCH 5.10.y-cip 02/12] clk: renesas: rzg2l: Add PLL5_4 clk mux support Biju Das
2023-12-07 10:54 ` [PATCH 5.10.y-cip 03/12] clk: renesas: rzg2l: Add DSI divider clk support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 04/12] clk: renesas: r9a07g044: Add M1 clock support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 05/12] clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 06/12] clk: renesas: r9a07g044: Add M3 Clock support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 07/12] clk: renesas: r9a07g044: Add M4 " Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 08/12] clk: renesas: r9a07g044: Add LCDC clock and reset entries Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 09/12] clk: renesas: r9a07g044: Add DSI " Biju Das
2023-12-07 10:55 ` Biju Das [this message]
2023-12-07 10:55 ` [PATCH 5.10.y-cip 11/12] clk: renesas: r9a07g044: Add POEG " Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 12/12] clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write Biju Das
2023-12-07 11:17 ` [PATCH 5.10.y-cip 00/12] Add display/dsi/gpt/poeg clk support Pavel Machek
2023-12-07 13:49 ` nobuhiro1.iwamatsu
2023-12-07 18:03 ` Pavel Machek
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