From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 04/12] clk: renesas: r9a07g044: Add M1 clock support
Date: Thu, 7 Dec 2023 10:55:00 +0000 [thread overview]
Message-ID: <20231207105508.171162-5-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20231207105508.171162-1-biju.das.jz@bp.renesas.com>
commit 60191843db7812dba4fdd2790a2d646721e13b21 upstream.
Add support for M1 clock which is sourced from FOUTPOSTDIV.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 6c7c8f25c284..bf98a95c7c27 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -40,6 +40,8 @@ enum clk_ids {
CLK_DIV_PLL3_C,
CLK_PLL4,
CLK_PLL5,
+ CLK_PLL5_FOUTPOSTDIV,
+ CLK_PLL5_FOUT1PH0,
CLK_PLL5_FOUT3,
CLK_PLL5_250,
CLK_PLL6,
@@ -52,6 +54,7 @@ enum clk_ids {
CLK_SD0_DIV4,
CLK_SD1_DIV4,
CLK_SEL_GPU2,
+ CLK_SEL_PLL5_4,
/* Module Clocks */
MOD_CLK_BASE,
@@ -77,12 +80,13 @@ static const struct clk_div_table dtable_1_32[] = {
/* Mux clock tables */
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
+static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
static const struct {
- struct cpg_core_clk common[44];
+ struct cpg_core_clk common[48];
#ifdef CONFIG_CLK_R9A07G054
struct cpg_core_clk drp[0];
#endif
@@ -124,6 +128,9 @@ static const struct {
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
DEF_MUX_RO(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2),
+ DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL),
+ DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),
+ DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4),
/* Core output clk */
DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
@@ -143,6 +150,7 @@ static const struct {
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8),
+ DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),
},
#ifdef CONFIG_CLK_R9A07G054
.drp = {
--
2.25.1
next prev parent reply other threads:[~2023-12-07 10:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-07 10:54 [PATCH 5.10.y-cip 00/12] Add display/dsi/gpt/poeg clk support Biju Das
2023-12-07 10:54 ` [PATCH 5.10.y-cip 01/12] clk: renesas: rzg2l: Add FOUTPOSTDIV " Biju Das
2023-12-07 10:54 ` [PATCH 5.10.y-cip 02/12] clk: renesas: rzg2l: Add PLL5_4 clk mux support Biju Das
2023-12-07 10:54 ` [PATCH 5.10.y-cip 03/12] clk: renesas: rzg2l: Add DSI divider clk support Biju Das
2023-12-07 10:55 ` Biju Das [this message]
2023-12-07 10:55 ` [PATCH 5.10.y-cip 05/12] clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 06/12] clk: renesas: r9a07g044: Add M3 Clock support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 07/12] clk: renesas: r9a07g044: Add M4 " Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 08/12] clk: renesas: r9a07g044: Add LCDC clock and reset entries Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 09/12] clk: renesas: r9a07g044: Add DSI " Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 10/12] clk: renesas: r9a07g044: Add GPT clock and reset entry Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 11/12] clk: renesas: r9a07g044: Add POEG clock and reset entries Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 12/12] clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write Biju Das
2023-12-07 11:17 ` [PATCH 5.10.y-cip 00/12] Add display/dsi/gpt/poeg clk support Pavel Machek
2023-12-07 13:49 ` nobuhiro1.iwamatsu
2023-12-07 18:03 ` Pavel Machek
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