From: Abhinav Kumar <quic_abhinavk@quicinc.com> To: <freedreno@lists.freedesktop.org>, Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Sean Paul <sean@poorly.run>, Marijn Suijten <marijn.suijten@somainline.org>, David Airlie <airlied@gmail.com>, "Daniel Vetter" <daniel@ffwll.ch> Cc: quic_jesszhan@quicinc.com, quic_parellan@quicinc.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v2 10/16] drm/msm/dpu: add CDM related logic to dpu_hw_ctl layer Date: Thu, 7 Dec 2023 21:06:35 -0800 [thread overview] Message-ID: <20231208050641.32582-11-quic_abhinavk@quicinc.com> (raw) In-Reply-To: <20231208050641.32582-1-quic_abhinavk@quicinc.com> CDM block will need its own logic to program the flush and active bits in the dpu_hw_ctl layer. Make necessary changes in dpu_hw_ctl to support CDM programming. changes in v2: - remove unused empty line - pass in cdm_num to update_pending_flush_cdm() Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 ++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 12 ++++++++ 2 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index e7b680a151d6..75b8a32389c3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -32,11 +32,13 @@ #define CTL_DSC_ACTIVE 0x0E8 #define CTL_WB_ACTIVE 0x0EC #define CTL_INTF_ACTIVE 0x0F4 +#define CTL_CDM_ACTIVE 0x0F8 #define CTL_FETCH_PIPE_ACTIVE 0x0FC #define CTL_MERGE_3D_FLUSH 0x100 #define CTL_DSC_FLUSH 0x104 #define CTL_WB_FLUSH 0x108 #define CTL_INTF_FLUSH 0x110 +#define CTL_CDM_FLUSH 0x114 #define CTL_INTF_MASTER 0x134 #define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4)) @@ -46,6 +48,7 @@ #define DPU_REG_RESET_TIMEOUT_US 2000 #define MERGE_3D_IDX 23 #define DSC_IDX 22 +#define CDM_IDX 26 #define INTF_IDX 31 #define WB_IDX 16 #define DSPP_IDX 29 /* From DPU hw rev 7.x.x */ @@ -107,6 +110,7 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) ctx->pending_wb_flush_mask = 0; ctx->pending_merge_3d_flush_mask = 0; ctx->pending_dsc_flush_mask = 0; + ctx->pending_cdm_flush_mask = 0; memset(ctx->pending_dspp_flush_mask, 0, sizeof(ctx->pending_dspp_flush_mask)); @@ -151,6 +155,10 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, ctx->pending_dsc_flush_mask); + if (ctx->pending_flush_mask & BIT(CDM_IDX)) + DPU_REG_WRITE(&ctx->hw, CTL_CDM_FLUSH, + ctx->pending_cdm_flush_mask); + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); } @@ -282,6 +290,13 @@ static void dpu_hw_ctl_update_pending_flush_wb(struct dpu_hw_ctl *ctx, } } +static void dpu_hw_ctl_update_pending_flush_cdm(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num) +{ + /* update pending flush only if CDM_0 is flushed */ + if (cdm_num == CDM_0) + ctx->pending_flush_mask |= BIT(CDM_IDX); +} + static void dpu_hw_ctl_update_pending_flush_wb_v1(struct dpu_hw_ctl *ctx, enum dpu_wb wb) { @@ -310,6 +325,12 @@ static void dpu_hw_ctl_update_pending_flush_dsc_v1(struct dpu_hw_ctl *ctx, ctx->pending_flush_mask |= BIT(DSC_IDX); } +static void dpu_hw_ctl_update_pending_flush_cdm_v1(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num) +{ + ctx->pending_cdm_flush_mask |= BIT(cdm_num - CDM_0); + ctx->pending_flush_mask |= BIT(CDM_IDX); +} + static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk) { @@ -513,6 +534,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, u32 intf_active = 0; u32 wb_active = 0; u32 mode_sel = 0; + u32 cdm_active = 0; /* CTL_TOP[31:28] carries group_id to collate CTL paths * per VM. Explicitly disable it until VM support is @@ -526,6 +548,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); + cdm_active = DPU_REG_READ(c, CTL_CDM_ACTIVE); if (cfg->intf) intf_active |= BIT(cfg->intf - INTF_0); @@ -543,6 +566,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->dsc) DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc); + + if (cfg->cdm) + DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm); } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, @@ -586,6 +612,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, u32 wb_active = 0; u32 merge3d_active = 0; u32 dsc_active; + u32 cdm_active; /* * This API resets each portion of the CTL path namely, @@ -621,6 +648,12 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, dsc_active &= ~cfg->dsc; DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active); } + + if (cfg->cdm) { + cdm_active = DPU_REG_READ(c, CTL_CDM_ACTIVE); + cdm_active &= ~cfg->cdm; + DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cdm_active); + } } static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx, @@ -654,12 +687,14 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1; ops->update_pending_flush_dsc = dpu_hw_ctl_update_pending_flush_dsc_v1; + ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1; } else { ops->trigger_flush = dpu_hw_ctl_trigger_flush; ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg; ops->update_pending_flush_intf = dpu_hw_ctl_update_pending_flush_intf; ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb; + ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm; } ops->clear_pending_flush = dpu_hw_ctl_clear_pending_flush; ops->update_pending_flush = dpu_hw_ctl_update_pending_flush; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 279ebd8dfbff..ff85b5ee0acf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -39,6 +39,7 @@ struct dpu_hw_stage_cfg { * @mode_3d: 3d mux configuration * @merge_3d: 3d merge block used * @intf_mode_sel: Interface mode, cmd / vid + * @cdm: CDM block used * @stream_sel: Stream selection for multi-stream interfaces * @dsc: DSC BIT masks used */ @@ -48,6 +49,7 @@ struct dpu_hw_intf_cfg { enum dpu_3d_blend_mode mode_3d; enum dpu_merge_3d merge_3d; enum dpu_ctl_mode_sel intf_mode_sel; + enum dpu_cdm cdm; int stream_sel; unsigned int dsc; }; @@ -166,6 +168,14 @@ struct dpu_hw_ctl_ops { void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx, enum dpu_dsc blk); + /** + * OR in the given flushbits to the cached pending_(cdm_)flush_mask + * No effect on hardware + * @ctx: ctl path ctx pointer + * @cdm_num: idx of cdm to be flushed + */ + void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num); + /** * Write the value of the pending_flush_mask to hardware * @ctx : ctl path ctx pointer @@ -239,6 +249,7 @@ struct dpu_hw_ctl_ops { * @pending_intf_flush_mask: pending INTF flush * @pending_wb_flush_mask: pending WB flush * @pending_dsc_flush_mask: pending DSC flush + * @pending_cdm_flush_mask: pending CDM flush * @ops: operation list */ struct dpu_hw_ctl { @@ -256,6 +267,7 @@ struct dpu_hw_ctl { u32 pending_merge_3d_flush_mask; u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0]; u32 pending_dsc_flush_mask; + u32 pending_cdm_flush_mask; /* ops */ struct dpu_hw_ctl_ops ops; -- 2.40.1
WARNING: multiple messages have this Message-ID (diff)
From: Abhinav Kumar <quic_abhinavk@quicinc.com> To: <freedreno@lists.freedesktop.org>, Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Sean Paul <sean@poorly.run>, Marijn Suijten <marijn.suijten@somainline.org>, David Airlie <airlied@gmail.com>, "Daniel Vetter" <daniel@ffwll.ch> Cc: <dri-devel@lists.freedesktop.org>, <quic_jesszhan@quicinc.com>, <quic_parellan@quicinc.com>, <linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v2 10/16] drm/msm/dpu: add CDM related logic to dpu_hw_ctl layer Date: Thu, 7 Dec 2023 21:06:35 -0800 [thread overview] Message-ID: <20231208050641.32582-11-quic_abhinavk@quicinc.com> (raw) In-Reply-To: <20231208050641.32582-1-quic_abhinavk@quicinc.com> CDM block will need its own logic to program the flush and active bits in the dpu_hw_ctl layer. Make necessary changes in dpu_hw_ctl to support CDM programming. changes in v2: - remove unused empty line - pass in cdm_num to update_pending_flush_cdm() Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 ++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 12 ++++++++ 2 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index e7b680a151d6..75b8a32389c3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -32,11 +32,13 @@ #define CTL_DSC_ACTIVE 0x0E8 #define CTL_WB_ACTIVE 0x0EC #define CTL_INTF_ACTIVE 0x0F4 +#define CTL_CDM_ACTIVE 0x0F8 #define CTL_FETCH_PIPE_ACTIVE 0x0FC #define CTL_MERGE_3D_FLUSH 0x100 #define CTL_DSC_FLUSH 0x104 #define CTL_WB_FLUSH 0x108 #define CTL_INTF_FLUSH 0x110 +#define CTL_CDM_FLUSH 0x114 #define CTL_INTF_MASTER 0x134 #define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4)) @@ -46,6 +48,7 @@ #define DPU_REG_RESET_TIMEOUT_US 2000 #define MERGE_3D_IDX 23 #define DSC_IDX 22 +#define CDM_IDX 26 #define INTF_IDX 31 #define WB_IDX 16 #define DSPP_IDX 29 /* From DPU hw rev 7.x.x */ @@ -107,6 +110,7 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) ctx->pending_wb_flush_mask = 0; ctx->pending_merge_3d_flush_mask = 0; ctx->pending_dsc_flush_mask = 0; + ctx->pending_cdm_flush_mask = 0; memset(ctx->pending_dspp_flush_mask, 0, sizeof(ctx->pending_dspp_flush_mask)); @@ -151,6 +155,10 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, ctx->pending_dsc_flush_mask); + if (ctx->pending_flush_mask & BIT(CDM_IDX)) + DPU_REG_WRITE(&ctx->hw, CTL_CDM_FLUSH, + ctx->pending_cdm_flush_mask); + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); } @@ -282,6 +290,13 @@ static void dpu_hw_ctl_update_pending_flush_wb(struct dpu_hw_ctl *ctx, } } +static void dpu_hw_ctl_update_pending_flush_cdm(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num) +{ + /* update pending flush only if CDM_0 is flushed */ + if (cdm_num == CDM_0) + ctx->pending_flush_mask |= BIT(CDM_IDX); +} + static void dpu_hw_ctl_update_pending_flush_wb_v1(struct dpu_hw_ctl *ctx, enum dpu_wb wb) { @@ -310,6 +325,12 @@ static void dpu_hw_ctl_update_pending_flush_dsc_v1(struct dpu_hw_ctl *ctx, ctx->pending_flush_mask |= BIT(DSC_IDX); } +static void dpu_hw_ctl_update_pending_flush_cdm_v1(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num) +{ + ctx->pending_cdm_flush_mask |= BIT(cdm_num - CDM_0); + ctx->pending_flush_mask |= BIT(CDM_IDX); +} + static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk) { @@ -513,6 +534,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, u32 intf_active = 0; u32 wb_active = 0; u32 mode_sel = 0; + u32 cdm_active = 0; /* CTL_TOP[31:28] carries group_id to collate CTL paths * per VM. Explicitly disable it until VM support is @@ -526,6 +548,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); + cdm_active = DPU_REG_READ(c, CTL_CDM_ACTIVE); if (cfg->intf) intf_active |= BIT(cfg->intf - INTF_0); @@ -543,6 +566,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->dsc) DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc); + + if (cfg->cdm) + DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm); } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, @@ -586,6 +612,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, u32 wb_active = 0; u32 merge3d_active = 0; u32 dsc_active; + u32 cdm_active; /* * This API resets each portion of the CTL path namely, @@ -621,6 +648,12 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, dsc_active &= ~cfg->dsc; DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active); } + + if (cfg->cdm) { + cdm_active = DPU_REG_READ(c, CTL_CDM_ACTIVE); + cdm_active &= ~cfg->cdm; + DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cdm_active); + } } static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx, @@ -654,12 +687,14 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1; ops->update_pending_flush_dsc = dpu_hw_ctl_update_pending_flush_dsc_v1; + ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1; } else { ops->trigger_flush = dpu_hw_ctl_trigger_flush; ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg; ops->update_pending_flush_intf = dpu_hw_ctl_update_pending_flush_intf; ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb; + ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm; } ops->clear_pending_flush = dpu_hw_ctl_clear_pending_flush; ops->update_pending_flush = dpu_hw_ctl_update_pending_flush; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 279ebd8dfbff..ff85b5ee0acf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -39,6 +39,7 @@ struct dpu_hw_stage_cfg { * @mode_3d: 3d mux configuration * @merge_3d: 3d merge block used * @intf_mode_sel: Interface mode, cmd / vid + * @cdm: CDM block used * @stream_sel: Stream selection for multi-stream interfaces * @dsc: DSC BIT masks used */ @@ -48,6 +49,7 @@ struct dpu_hw_intf_cfg { enum dpu_3d_blend_mode mode_3d; enum dpu_merge_3d merge_3d; enum dpu_ctl_mode_sel intf_mode_sel; + enum dpu_cdm cdm; int stream_sel; unsigned int dsc; }; @@ -166,6 +168,14 @@ struct dpu_hw_ctl_ops { void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx, enum dpu_dsc blk); + /** + * OR in the given flushbits to the cached pending_(cdm_)flush_mask + * No effect on hardware + * @ctx: ctl path ctx pointer + * @cdm_num: idx of cdm to be flushed + */ + void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num); + /** * Write the value of the pending_flush_mask to hardware * @ctx : ctl path ctx pointer @@ -239,6 +249,7 @@ struct dpu_hw_ctl_ops { * @pending_intf_flush_mask: pending INTF flush * @pending_wb_flush_mask: pending WB flush * @pending_dsc_flush_mask: pending DSC flush + * @pending_cdm_flush_mask: pending CDM flush * @ops: operation list */ struct dpu_hw_ctl { @@ -256,6 +267,7 @@ struct dpu_hw_ctl { u32 pending_merge_3d_flush_mask; u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0]; u32 pending_dsc_flush_mask; + u32 pending_cdm_flush_mask; /* ops */ struct dpu_hw_ctl_ops ops; -- 2.40.1
next prev parent reply other threads:[~2023-12-08 5:07 UTC|newest] Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-12-08 5:06 [PATCH v2 00/16] Add CDM support for MSM writeback Abhinav Kumar 2023-12-08 5:06 ` [PATCH v2 01/16] drm/msm/dpu: add formats check for writeback encoder Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 5:06 ` [PATCH v2 02/16] drm/msm/dpu: rename dpu_encoder_phys_wb_setup_cdp to match its functionality Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 5:06 ` [PATCH v2 03/16] drm/msm/dpu: fix writeback programming for YUV cases Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 11:11 ` Dmitry Baryshkov 2023-12-08 11:11 ` Dmitry Baryshkov 2023-12-08 5:06 ` [PATCH v2 04/16] drm/msm/dpu: move csc matrices to dpu_hw_util Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 11:12 ` Dmitry Baryshkov 2023-12-08 11:12 ` Dmitry Baryshkov 2023-12-08 16:24 ` Abhinav Kumar 2023-12-08 16:24 ` Abhinav Kumar 2023-12-08 16:27 ` Dmitry Baryshkov 2023-12-08 16:27 ` Dmitry Baryshkov 2023-12-08 16:35 ` Abhinav Kumar 2023-12-08 16:35 ` Abhinav Kumar 2023-12-08 16:40 ` Dmitry Baryshkov 2023-12-08 16:40 ` Dmitry Baryshkov 2023-12-08 5:06 ` [PATCH v2 05/16] drm/msm/dpu: add cdm blocks to sc7280 dpu_hw_catalog Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 11:13 ` Dmitry Baryshkov 2023-12-08 11:13 ` Dmitry Baryshkov 2023-12-08 11:19 ` Dmitry Baryshkov 2023-12-08 11:19 ` Dmitry Baryshkov 2023-12-11 21:16 ` Abhinav Kumar 2023-12-11 21:16 ` Abhinav Kumar 2023-12-11 21:31 ` Dmitry Baryshkov 2023-12-11 21:31 ` Dmitry Baryshkov 2023-12-11 21:32 ` Abhinav Kumar 2023-12-11 21:32 ` Abhinav Kumar 2023-12-11 21:42 ` Dmitry Baryshkov 2023-12-11 21:42 ` Dmitry Baryshkov 2023-12-11 21:48 ` Abhinav Kumar 2023-12-11 21:48 ` Abhinav Kumar 2023-12-12 6:49 ` Dmitry Baryshkov 2023-12-12 6:49 ` Dmitry Baryshkov 2023-12-12 17:12 ` Dmitry Baryshkov 2023-12-12 17:12 ` Dmitry Baryshkov 2023-12-08 5:06 ` [PATCH v2 06/16] drm/msm/dpu: add cdm blocks to sm8250 dpu_hw_catalog Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 11:20 ` Dmitry Baryshkov 2023-12-08 11:20 ` Dmitry Baryshkov 2023-12-08 5:06 ` [PATCH v2 07/16] drm/msm/dpu: add dpu_hw_cdm abstraction for CDM block Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 12:06 ` Dmitry Baryshkov 2023-12-08 12:06 ` Dmitry Baryshkov 2023-12-08 17:08 ` Abhinav Kumar 2023-12-08 17:08 ` Abhinav Kumar 2023-12-08 18:17 ` Dmitry Baryshkov 2023-12-08 18:17 ` Dmitry Baryshkov 2023-12-10 10:53 ` kernel test robot 2023-12-10 10:53 ` kernel test robot 2023-12-08 5:06 ` [PATCH v2 08/16] drm/msm/dpu: add cdm blocks to RM Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 11:26 ` Dmitry Baryshkov 2023-12-08 11:26 ` Dmitry Baryshkov 2023-12-08 5:06 ` [PATCH v2 09/16] drm/msm/dpu: add support to allocate CDM from RM Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 11:33 ` Dmitry Baryshkov 2023-12-08 11:33 ` Dmitry Baryshkov 2023-12-08 5:06 ` Abhinav Kumar [this message] 2023-12-08 5:06 ` [PATCH v2 10/16] drm/msm/dpu: add CDM related logic to dpu_hw_ctl layer Abhinav Kumar 2023-12-08 11:34 ` Dmitry Baryshkov 2023-12-08 11:34 ` Dmitry Baryshkov 2023-12-10 12:29 ` kernel test robot 2023-12-10 12:29 ` kernel test robot 2023-12-08 5:06 ` [PATCH v2 11/16] drm/msm/dpu: add support to disable CDM block during encoder cleanup Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 11:36 ` Dmitry Baryshkov 2023-12-08 11:36 ` Dmitry Baryshkov 2023-12-08 5:06 ` [PATCH v2 12/16] drm/msm/dpu: add an API to setup the CDM block for writeback Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 11:52 ` Dmitry Baryshkov 2023-12-08 11:52 ` Dmitry Baryshkov 2023-12-08 17:27 ` Abhinav Kumar 2023-12-08 17:27 ` Abhinav Kumar 2023-12-08 20:55 ` Dmitry Baryshkov 2023-12-08 20:55 ` Dmitry Baryshkov 2023-12-08 22:48 ` Abhinav Kumar 2023-12-08 22:48 ` Abhinav Kumar 2023-12-10 14:06 ` kernel test robot 2023-12-10 14:06 ` kernel test robot 2023-12-08 5:06 ` [PATCH v2 13/16] drm/msm/dpu: plug-in the cdm related bits to writeback setup Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 5:06 ` [PATCH v2 14/16] drm/msm/dpu: reserve cdm blocks for writeback in case of YUV output Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 11:54 ` Dmitry Baryshkov 2023-12-08 11:54 ` Dmitry Baryshkov 2023-12-08 16:33 ` Abhinav Kumar 2023-12-08 16:33 ` Abhinav Kumar 2023-12-08 16:38 ` Dmitry Baryshkov 2023-12-08 16:38 ` Dmitry Baryshkov 2023-12-08 16:50 ` Abhinav Kumar 2023-12-08 16:50 ` Abhinav Kumar 2023-12-08 5:06 ` [PATCH v2 15/16] drm/msm/dpu: introduce separate wb2_format arrays for rgb and yuv Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 11:44 ` Dmitry Baryshkov 2023-12-08 11:44 ` Dmitry Baryshkov 2023-12-08 17:53 ` Abhinav Kumar 2023-12-08 17:53 ` Abhinav Kumar 2023-12-08 20:45 ` Dmitry Baryshkov 2023-12-08 20:45 ` Dmitry Baryshkov 2023-12-08 23:09 ` Abhinav Kumar 2023-12-08 23:09 ` Abhinav Kumar 2023-12-09 1:10 ` Dmitry Baryshkov 2023-12-09 1:10 ` Dmitry Baryshkov 2023-12-08 5:06 ` [PATCH v2 16/16] drm/msm/dpu: add cdm blocks to dpu snapshot Abhinav Kumar 2023-12-08 5:06 ` Abhinav Kumar 2023-12-08 12:14 ` [PATCH v2 00/16] Add CDM support for MSM writeback Dmitry Baryshkov 2023-12-08 17:40 ` Abhinav Kumar 2023-12-08 20:49 ` Dmitry Baryshkov
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