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From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <acme@kernel.org>, <adrian.hunter@intel.com>,
	<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
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	<namhyung@kernel.org>, <palmer@dabbelt.com>,
	<paul.walmsley@sifive.com>, <peterlin@andestech.com>,
	<peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<rdunlap@infradead.org>, <robh+dt@kernel.org>,
	<samuel@sholland.org>, <sunilvl@ventanamicro.com>,
	<tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>,
	<wens@csie.org>, <will@kernel.org>, <ycliang@andestech.com>,
	<inochiama@outlook.com>
Subject: [PATCH v5 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b
Date: Wed, 13 Dec 2023 15:02:57 +0800	[thread overview]
Message-ID: <20231213070301.1684751-13-peterlin@andestech.com> (raw)
In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com>

xtheadpmu stands for T-Head Performance Monitor Unit extension.
Based on the added T-Head PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v4 -> v5:
  - New patch
---
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index aec6401a467b..8c0143f0a01b 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -29,7 +29,7 @@ cpu0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
-- 
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <acme@kernel.org>, <adrian.hunter@intel.com>,
	<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
	<andre.przywara@arm.com>, <anup@brainfault.org>,
	<aou@eecs.berkeley.edu>, <atishp@atishpatra.org>,
	<conor+dt@kernel.org>, <conor.dooley@microchip.com>,
	<conor@kernel.org>, <devicetree@vger.kernel.org>,
	<dminus@andestech.com>, <evan@rivosinc.com>,
	<geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>,
	<irogers@google.com>, <jernej.skrabec@gmail.com>,
	<jolsa@kernel.org>, <jszhang@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>,
	<linux-renesas-soc@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-sunxi@lists.linux.dev>,
	<locus84@andestech.com>, <magnus.damm@gmail.com>,
	<mark.rutland@arm.com>, <mingo@redhat.com>, <n.shubin@yadro.com>,
	<namhyung@kernel.org>, <palmer@dabbelt.com>,
	<paul.walmsley@sifive.com>, <peterlin@andestech.com>,
	<peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	<rdunlap@infradead.org>, <robh+dt@kernel.org>,
	<samuel@sholland.org>, <sunilvl@ventanamicro.com>,
	<tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>,
	<wens@csie.org>, <will@kernel.org>, <ycliang@andestech.com>,
	<inochiama@outlook.com>
Subject: [PATCH v5 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b
Date: Wed, 13 Dec 2023 15:02:57 +0800	[thread overview]
Message-ID: <20231213070301.1684751-13-peterlin@andestech.com> (raw)
In-Reply-To: <20231213070301.1684751-1-peterlin@andestech.com>

xtheadpmu stands for T-Head Performance Monitor Unit extension.
Based on the added T-Head PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v4 -> v5:
  - New patch
---
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index aec6401a467b..8c0143f0a01b 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -29,7 +29,7 @@ cpu0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2023-12-13  7:05 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-13  7:02 [PATCH v5 00/16] Support Andes PMU extension Yu Chien Peter Lin
2023-12-13  7:02 ` Yu Chien Peter Lin
2023-12-13  7:02 ` [PATCH v5 01/16] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13  7:02 ` [PATCH v5 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13 14:28   ` Anup Patel
2023-12-13 14:28     ` Anup Patel
2023-12-13 15:19     ` Anup Patel
2023-12-13 15:19       ` Anup Patel
2023-12-19  7:43       ` Yu-Chien Peter Lin
2023-12-19  7:43         ` Yu-Chien Peter Lin
2023-12-13  7:02 ` [PATCH v5 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13 14:45   ` Anup Patel
2023-12-13 14:45     ` Anup Patel
2023-12-13 15:44     ` Yu-Chien Peter Lin
2023-12-13 15:44       ` Yu-Chien Peter Lin
2023-12-13 15:48       ` Anup Patel
2023-12-13 15:48         ` Anup Patel
2023-12-13  7:02 ` [PATCH v5 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13  7:02 ` [PATCH v5 05/16] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13  7:02 ` [PATCH v5 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13  7:02 ` [PATCH v5 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13 15:27   ` Conor Dooley
2023-12-13 15:27     ` Conor Dooley
2023-12-13 15:27     ` Conor Dooley
2023-12-13 15:32     ` Conor Dooley
2023-12-13 15:32       ` Conor Dooley
2023-12-13 15:32       ` Conor Dooley
2023-12-13  7:02 ` [PATCH v5 08/16] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13  7:02 ` [PATCH v5 09/16] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13 15:26   ` Conor Dooley
2023-12-13 15:26     ` Conor Dooley
2023-12-13 15:26     ` Conor Dooley
2023-12-13  7:02 ` [PATCH v5 10/16] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13  7:02 ` [PATCH v5 11/16] riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13  7:02 ` Yu Chien Peter Lin [this message]
2023-12-13  7:02   ` [PATCH v5 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b Yu Chien Peter Lin
2023-12-13 15:23   ` Conor Dooley
2023-12-13 15:23     ` Conor Dooley
2023-12-13 15:23     ` Conor Dooley
2023-12-13  7:02 ` [PATCH v5 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042 Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13 15:24   ` Conor Dooley
2023-12-13 15:24     ` Conor Dooley
2023-12-13 15:24     ` Conor Dooley
2023-12-13  7:02 ` [PATCH v5 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520 Yu Chien Peter Lin
2023-12-13  7:02   ` Yu Chien Peter Lin
2023-12-13 15:23   ` Conor Dooley
2023-12-13 15:23     ` Conor Dooley
2023-12-13 15:23     ` Conor Dooley
2023-12-13  7:03 ` [PATCH v5 15/16] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2023-12-13  7:03   ` Yu Chien Peter Lin
2023-12-13 15:24   ` Conor Dooley
2023-12-13 15:24     ` Conor Dooley
2023-12-13 15:24     ` Conor Dooley
2023-12-13  7:03 ` [PATCH v5 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2023-12-13  7:03   ` Yu Chien Peter Lin

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